LECTURE EIGHT DIGITAL ELECTRONICS

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LECTURE EIGHT DIGITAL ELECTRONICS
Dr Richard ReillyDept. of Electronic
Electrical EngineeringRoom 153, Engineering
Building
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NMOS Logic Elements

• MOS technology is the basis for most LSI and all
  VLSI and ULSI digital memory and microprocessor
  circuits
•  
• The most important advantage of MOS circuits
  over bipolar circuits for LSI is that more
  transistors and more circuit functions may be
  successfully fabricated on a single chip with MOS
  technology.

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NMOS Logic Elements

• There are 3 reasons for this
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• 1.   An individual MOS transistor occupies less
  chip area
•  
• 2.   MOS fabrication process involves fewer
  steps and as a result achieves fewer critical
  defects per unit chip area than in bipolar
  circuit fabrication Þ make feasible somewhat
  larger chips in MOS technology
•  
• 3.   Dynamic circuit techniques that require
  fewer transistors to realise a given circuit
  function are practical in MOS technology.
•  
• Þ LSI (and thus VLSI) circuits significantly
  cheaper to manufacture than bipolar circuits of
  equivalent function.

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NMOS Logic Elements

• What are important issues of MOS Devices for
  Digital Electronics ?
•  
•      DC and Transient characteristics are
  important and critical to LSI digital circuit
  design.

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Alternative MOS processes

• 1st MOS circuit, made in Metal-Gate p-channel
  (PMOS) technology
•        Required special supply voltage (-9V, -12
  V)
•        Functional only at very low digital data
  rates 200k? 1Mb/sec
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• 2nd MOS circuit, made in Silicon-Gate n-channel
  (NMOS) technology
•        Required only a single supply voltage
  (5V)
•        Operates at data rates ? 40Mb/sec

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Alternative MOS processes

• A significant reduction in the internal
  dimensions of individual devices results in a
  very sharp improvement in circuit speed.
•  
• Bipolar circuit speed improves only gradually as
  internal dimensions are similarly reduced.
•  
• An important limitation of MOS circuit is in
  driving high currents and high voltages
• Standard LSI processes limited to 5 10 V max
  operating voltage
• Are inefficient when driving more than 20mA into
  a load.

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Alternative MOS processes

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• This is the main speed-limiting factor in digital
  systems employing data busses that exhibit high
  capacitance
• As bipolar digital circuits, particularly ECL,
  can drive highly capacitive loads and terminated
  transmission lines at high speeds
• ECL normally used when off-chip data rates of
  20Mb/sec and higher
• E.g. Opto-electronic and High Speed Signal
  Processors

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Alternative MOS processes

• Metal-Gate PMOS and NMOS are the original
  versions of the MOS process that are not much
  used in modern designs.
• The prevalent version of MOS technology is
• Self-Aligned Silicon Gate NMOS
• Modern version employ a technique known as local
  oxidation to increase circuit density and
  performance

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Alternative MOS processes

• Complementary MOS (CMOS) technologies provide
  both n-channel and p-channel devices in one chip,
  at the expense of some increased fabrication
  complexity and chip area compared to NMOS.
• The great advantage of CMOS is that they can be
  designed for essentially zero power consumption
  in steady-state condition for both logic states
• Power is consumed only when circuit switches
  between logic states

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Two types of CMOS exist

• 1.   Metal-Gate CMOS
•        Widely used
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• 2.   Silicon-Gate CMOS
•        More complex to manufacture
•        Offers significantly higher circuit
  density
•        Better high-speed performance when used
  in VLSI
• e.g, CMOS memories and microprocessors

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MOS Modes of Operation

• The circuit symbol for the n-channel MOS is shown
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• The threshold voltage in an n-channel MOS device,
  for Drain-Source current to flow
•              
• and

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What is the Threshold voltage and what is it
dependent on ?

• Dependent on the physical dimensions and
  parameters of the MOS device
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• ? For the enhancement only NMOS transistor VT is
  positive
• ? For the enhancement-depletion NMOS
  transistor VT is negative
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• For PMOS devices, the Threshold Voltage is
  opposite in sign to the corresponding NMOS

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Cut-off

• If for an NMOS device
• Þ device is in cut-off
• Þ
• Linear
• If for an NMOS device
• Þ for
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• For Þ NMOS in linear mode
• Þ
• where ? is the gain factor or transconductance
  parameter