LISATek

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LISATek

• Hui-Chun Wu
• Yung-Shuo Lin

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References

• A. Hoffmann et al., A Novel Methodology for the
  Design of Application-Specific Instruction-Set
  Processors (ASIPs) Using a Machine Description
  Language IEEE Transactions on CAD of Integrated
  Circuits and Systems, Vol.20, No. 11, Nov. 2001

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Design Phases

• Architecture Exploration
• Best match architecture for the application
• Architecture Implementation
• Obtain synthesizable HDL
• Application Software Design
• Set of production-quality software
• System Integration and Verification
• Develop system co-simulation environment

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Related Works

• Traditional HDL (VHDL, Verilog, )
• Too slow for full cycle-accurate simulation
• Maril
• Too coarse for cycle-accurate simulation
• nML, MetaCore
• No pipelining implementation support
• EXPRESSION, FlexWare2, PEAS-III
• Incomplete implementation
• Xtensa
• Too powerful for application-specific processors

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LISA

• Language for Instruction-Set Architectures
• Aim to describe the programmable architecture
  peripherals and interfaces
• Compose of resources and operations
• Resources represent storage objects
• Operations represent behaviors and structures

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LISA Models

• Memory Model
• Resource Model
• Instruction-Set Model
• Behavioral Model
• Timing Model
• Microarchitecture Model

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LISA Model Example

• RESOURCE
• REGISTER unsigned int R(0..7)6
• DATA_MEMORY signed int RAM(0..15)
• OPERATION NEG_RM
• BEHAVIOR
• USES (IN R
• OUT RAM)
• / C-code /
• RAMaddress (-1)Rindex

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LISA Model Example

• OPERATION COMPARE_IMM
• DECLARE
• LABEL index
• GROUP src1, dest register
• CODING 0b0011 index0bx5 src1 dest
• SYNTAX CMPsrc1 , index , dest
• SEMANTICS CMP (dest,src1,index)

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LISA Processor Design Platform

• Hardware Designer
• Generate synthesizable HDL and profiling data
• Software Designer
• Generate C compiler, assemblers, linkers,
  simulator
• System Integrator
• Provide API to allow complete control of the
  simulator

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Software Tools

• HLL C compiler
• Assembler
• Support mnemonic-based instruction as well as
  C-like algebraic assembly syntax
• Linker
• Support various external memory configuration

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Software Tools

• Simulator
• Interpretive simulation
• Compiled Simulation
• Static Scheduling
• Dynamic Scheduling

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Limitations

• LISA uses zero-delay model
• Event between steps are ignored
• LISA lacks multilevel cache implementation
  support
• Claim can be fix with C/C models
• Compiler generate code quality is fair
• Admit that design methodology can only be carry
  out effectively with a good compiler

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Limitations

• Datapath within synthesizable HDL code needs to
  be written manually
• Only can synthesis LISA language elements
• Architectural properties are not synthesizable
• Includes pipelined functional units and multiple
  instruction word decoders