Data Converters for Portable Devices

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Data Convertersfor Portable Devices
(CORE/CWC Review, November 3, 2000)
Bang-Sup Song, ECE Dept., UCSD
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Executive Summary
Just started with two new students. Prototype
systems are being sketched. Preliminary study on
background offset-trimming distributed
preamplifiers has been done. Simulations of
candidate S/H and T/H are underway. The design
will be completed by June 30, 2001.
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Past Year Accomplishments and Progress
Two Ph.D. students started this September. Study
to implement a pipelined, subranging,
interpolating ADC with reference and offset
errors trimmed in background. Investigate
linear S/H and T/H circuits with sampling switch
linearization and clock edge enhancement for low
jitter.
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Software Radio
LNA
X
BPF
ADC
DSP
DAC
LPF
R
DAC
LPF

SYN
...
RF
ADC
LPF
T
PA
X
BPF
DAC
ADC
LPF
gt90dB SFDR (15b linear) ADC and DAC _at_ 100MS/s
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High-Speed CMOS ADCs
Resolution Speed
Limit Accuracy Flash
6b 800MS/s S/H
-
Comparator Subranging/ 8b
150MS/s Reference
- Interpolation
Offset Folding/ 10b
50MS/s Reference Averaging Interpola
tion
Offset Pipeline 12b
65MS/s MDAC Trim Pipeline/
13b 40MS/s Reference
Offset Folding
Offset Calibration
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High-Speed ADC Family Tree
Subranging Interpolation
Interpolation
(save preamps)
Folding Interpolation
Flash
Folding
(save comps)
Subranging Folding
Subranging
(save preamps comps)
Multi-step or Pipeline
Interleaving, averaging, and pipelining are
common.
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Single-Residue vs. Multi-Residue
Single-residue Multi-residue Matching high
low Amp gain high low Settling accurate le
ss accurate Resolution high low Speed slow
fast Complexity simple complex
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Why not Single-Residue?
Single-residue architectures are simple, and have
been widely used. Most designers in industry and
academia are trying to speed up pipelined ADCs
for 100MS/s either with trimming, calibration, or
randomization. But single-residue ADCs need
high-gain amplifiers that can settle within
5nsec. Bipolar, BiCMOS, or SiGe may be a better
choice than CMOS.
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Then is Multi-Residue easy?
No. multi-residue systems are far more
complicated and have so many error sources. They
have only been used for low resolution but
high speed. However, multi-residue systems can
be configured so that their weakness can be
overcome. The gain mismatch and interpolation
errors can be reduced by resolving more bits
before interpolation, and the reference and
offset errors can be trimmed in background.
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Flash vs. Subranging Residues
Vout
Save of preamps and comparators, but
need comparator time.
Vin
Vout
Vin
Input range
Input range
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Flash vs. Folding Residues
Vout
Save of comparators and comparator time,
but need many preamps.
Vin
Vout
Vin
Input range
Input range
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Dual-Residue Subranging Pipeline
Vref Vin 0
0
low gain, slow settling - reference, offset,
comparator time, gain matching
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Subranging/Interpolation/Pipeline
Vref Vin 0
0
low gain, slow settling, comparator time -
reference, offset, too many preamps, gain matching
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Pipelining/Folding/Interpolation
Vref Vin 0
0
F o l d e r
F o l d e r
F o l d e r
low gain, slow settling, comparator time -
reference, offset, too many preamps, gain matching
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Multi-Residue Accuracy
Gain mismatch Interpolation error

• For accurate zero crossings
• - Accurate reference
• Zero or constant offset
• Amplifier gain matching
• Accurate interpolation

Vout
Vin
Reference Offset error
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Gain Matching Requirement
Preamp outputs
INL error (LSB)
aN/4
Vout
1
1a
Vin
0 1 2 3 N-2 N-1 N
0 N/2 N of
interpolated points
Interpolated outputs
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Type I - Subranging/
Vref Vin 0
low gain, slow settling, gain matching -
reference, offset, comparator time
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Type II - Pipelining/
Vref Vin 0
F o l d e r
F o l d e r
low gain, slow settling, gain matching,
comparator time - reference, offset, comparator
time for the 1st stage
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High-Speed/Resolution Ideas
Reason Type I Type II To simplify Subrangin
g Subranging To speed up Pipelining Pipelinin
g To save preamps Interpolation Interpolation T
o save latch time Folding To make it
linear Calibration Calibration
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13b 40MS/s CMOS ADC (Type II)

• First CMOS 13b Folder
• Subranging, Pipelining,
• Folding, Interpolation
• Background Trimming
• 82dB SFDR
• 0.5um CMOS
• - ISSCC 2000

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Differential Nonlinearity
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Integral Nonlinearity
INL after offset self-trimming
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10
5
INL LSB
0
-5
-10
-15
0
1000
2000
3000
4000
5000
6000
7000
8000
Code
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Prototype ADC System (Type I)
0 0
S/H
In
A/D
A/D
A/D
T/H
T/H
7 to 1 M U X
7 to 1 M U X
7 to 1 M U X
16x 8Rs
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Project Goals
Demonstrate a 1.5V, gt14b, gt50MS/s ADC in
CMOS. Develop a linear T/H and S/H for the
ADC. Introduce background offset-trimming for
the DAC.