14'2 Floorplanning

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14.2 Floorplanning
Final stage of layout floorplan

• Floorplan
• placement of bondpads
• Locations and shapes of cells
• serves as a guide for constructing the Padring,
  and as a template for assembling the top level
  layout once the cells are completed.

• Info required
• area estimates of each cell and whole die
• Complete listing of all pads and the order of
  their placement
• Example

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Example of the info needed for a small analog IC
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• Sketch out the padring For example,
• assume a square aspect ratio, 1.33mm2 1.153mm
  x 1.153mm
• round off to nearest increment according to
  Stepper (photomask vendor)
• older steppers in mils 1153 um 46 mils
  (1168.4 um)
• newer steepr in metric units
• Choose the leadframe Example, 8-pin DIP

Mount pad
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• mount pad
• die size lt mount pad side
• give 125 um allowance per side ? 1.5 x 2.0 mm
  1.375 x 1.875 mm ? easily the 1.153 x 1.153mm
  die
• Choose the smallest leadframe that will
  accommodate the die because too large leadframes
  may reduce assembly yield due to wiresweep and
  sag
• bond pad arrangement for shortest and most
  direct bondwire routing
• show location of scribe streets
• process puts specific requirement (bottom/left,
  top/right, all sides, etc.)
• Floorplan sketch example

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• floorplan sketch example
• show scribe streets, cell size, wire-to-pin,
  etc.
• the 20 area for routing is in the two narrow
  vertical strips
• bondpad location by placing floorplan on
  leadframe drawing

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• bondpad placement example
• compare the bondpad location with pin location
• note the location of the two power pads _at_ top
  bottom
• power pad locations run to all 3 blocks, min.
  interference, ..

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• check high-current leads
• as short as possible for min. R
• anticipated location of each lead should be
  marked on floorplan
• equiv. DC current value should be marked

• note the VCC lead over bias cell
• If BIAS block must use Metal-2, then the VCC
  lead can slide into channel
• In practice, VEE leads are part of scribe-seal
  metallization
• use scribe-seal metal. Fin power and GND
  return
• another width of metal around the
• periphery, abutting the scribe seal
• substrate contacts in scribe seal

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• High-current lead width due to electromigration
• Wmin 1012 IDC/Jmax t
• Ex) Jmax 5E5 A/cm2, max. allowed t 8,000
  Angstrom IDC 60 mA 0.06 A Wmin 1012
  0.06 / (5E5 8,000) 15 um
• Sheet Resistance Rs
• Rs 1E8 r Wcm / t A
• Ex) r 2.8E-6 Wcm for Al with 0.5 Cu and 2
  SI t 8,000 Angstrom
• Rs 1E8 2.8E-6 / 8,000 35 mW/sq.
• Ex) The 15-um wide 60-mA VCC lead runs 1,000 um
  ? 1,000/15 67 squares ? 67 sq. 35 mW/sq
  2.3 W ? 2.3W 60 mA 140 mV drop.
• IF both Amps connect to the same VCC lead, THEN
  cross-talk. ? Consider using Kelvin connection
  (Sec.14.3.2)
• IF VIAS must be used in Power lead, THEN
• electromigration can fail VIAS the same way as
  in metal lead
• Ex) If a 4-um wide VIA can carry 4 mA/um and a
  VIA has 0.1 W, THEN
• a VIA conducts 4 mA/um 4 um 16 mA. A 1-Amp
  lead must have 1/0.016 63 VIAs and 0.1W / 63
  2 mW.

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• Routing Channel placement of blocks, be
  careful the choke points!

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