MultiProject Reticle Floorplanning and Wafer Dicing

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Multi-Project Reticle Floorplanning and Wafer
Dicing
Andrew B. Kahng1 Ion I. Mandoiu2 Qinke Wang1
Xu Xu1 Alex Zelikovsky3
(1) CSE Department, University of California at
San Diego
(2) CSE Department, University of Connecticut
(3) CS Department, Georgia State University
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Introduction to Multi-Project Wafer
Design flow
Side-to-side wafer dicing problem
Reticle floorplanning and wafer dicing problem
Experimental results
Conclusions and future research directions
3
Mask cost 1M for 90 nm technology
Wafer cost 4K per wafer
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Share rising costs of mask tooling between
multiple prototype and low production volume
designs ? Multi-Project Wafer
Image courtesy of CMP and EuroPractice
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Introduced in late 1970s and early 1980s
Companies MOSIS, CMP, TSMC
Several approaches proposed
Chen et al. give bottom-left fill algorithm, 2003
Anderson et al. proposed grid packing algorithm,
2003
Tools MaskCompose, GTMuch
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Introduction to Multi-Project Wafer
Design flow
Side-to-side wafer dicing problem
Reticle floorplanning and wafer dicing problem
Experimental results
Conclusions and future research directions
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• Unique designs

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• Custom designs
• Partition between reticles

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• Custom designs
• Partition between shuttles
• Reticle placement

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• Custom designs
• Partition between shuttles
• Reticle placement
• Stepper shot-map

shot-map
print
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• Custom designs
• Partition between shuttles
• Reticle placement
• Stepper shot-map
• Dicing plan design

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• Custom designs
• Partition between shuttles
• Reticle placement
• Stepper shot-map
• Dicing plan design

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• Custom designs
• Partition between shuttles
• Reticle placement
• Stepper shot-map
• Dicing plan design
• Extract dice

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Introduction to Multi-Project Wafer
Design flow
Side-to-side wafer dicing problem
Reticle floorplanning and wafer dicing problem
Experimental results
Conclusions and future research directions
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Side-to-side dicing is the prevalent wafer dicing
technology
Sliced out

• A die is sliced out if and only if
• Four edges are on the cut lines
• No cut lines pass through the die

Dicing is complex for MPW. Most dice will be
destroyed if placement is not well aligned.
Dicing is easy for standard wafers. All dice will
be sliced out.
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• Given
• reticle placement
• wafer shot-map
• required volume for each die
• Find
• Set of horizontal and vertical cut lines (dicing
  plan)

• To Minimize
• w wafers used

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dice are in H-Conflict if they can not be sliced
out horizontally.
1 and 2 are in H-conflict
Die 1 is in H-Conflict with entire row of Die 2.
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• A horizontal Dicing Plan (DP) is a set of lines
  which dice one
• row of prints
• A set of dice which are pairwise not in
  H-conflict can be
• sliced out by a DP
• We seek such maximal horizontal independent sets

The dicing plan which slices out dice 1 and 4
MHIS (MVIS) set of all horizontal (vertical) DPs
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• Two dice are in H-conflict iff their vertical
  projections overlap
• ? Interval graph, which can be optimally
  colored
• All dice of the same color can be horizontally
  sliced out

2
1
1
2
4
3
3
4
2
1
4
3
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• Assume the wafer is a rectangular array of
  prints.
• fH rows (with DP H)

one DP per row
rows whose dicing plans slice out Di
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• Assume the wafer is a rectangular array of
  prints.
• gV columns (with DP V)

one DP per column
columns whose dicing plans slice out Di
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N(Di) required copies of die Di z1/( wafer)
Must slice out at least the required volume
copies sliced out
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• Assume the wafer is a rectangular array of
  prints.
• fH rows (with DP H)
• gV columns (with DP V)
• N(Di) required copies of die Di

Maximize z 1/( wafers)
Subject to
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One DP per row
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One DP per column
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The print at rth row and cth column is diced by
DP H and V iff we use H at the rth row and V at
the cth column
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Sliced out at least required volume
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Maximize z 1/( wafers)
Subject to
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• Choose initial dicing plan using interval graph
  coloring

DP2
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• Choose initial dicing plan using interval graph
  coloring

• In each iteration, first check whether z will
  increase by changing the dicing plan for one row
  or column

DP1,,DPMHIS
DP2
DP1,,DPMVIS
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• Choose initial dicing plan using interval graph
  coloring

• In each iteration, first check whether z will
  increase by changing the dicing plan for one row
  or column

• Choose one dicing plan for one new row or column
  which maximizes z

DP1
DP3
DP1,,DPMHIS
DP2
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• Ten random testcases with different numbers of
  dice
• Required production volume is 40 for all dice
• Assume a wafer has 10 rows and 10 columns of
  prints
• We used CPLEX 8.100 to solve LP
• We used LINGO 6.0 to solve NLP
• We implemented the IASA heuristic in C
• All tests are run on an Intel Xeon 2.4GHz CPU

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• Performance of IASA is much better

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Introduction to Multi-Project Wafer
Design flow
Side-to-side wafer dicing problem
Reticle floorplanning and wafer dicing problem
Experimental results
Conclusions and future research directions
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• Min-area floorplan
• ? high wafer cost

1
2
1
2
1
2
3
3
4
4
3
4
1
2
1
2
40 wafers needed for 40 copies
3
3
4
4
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• Min-area floorplan
• ? High wafer cost

1
2
1
2
1
2
3
3
4
4
3
4
1
2
1
2
40 wafers needed for 40 copies
3
3
4
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• Diagonal floorplan
• Larger reticle
• High wafer cost

4
2
1
3
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• Min-area floorplan
• ? high wafer cost

1
2
1
2
1
2
3
3
4
4
3
4
1
2
1
2
40 wafers needed for 40 copies
3
3
4
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• Diagonal floorplan
• ? high mask cost

4
2
1
3
2
2
1
1
4
3
4
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• Good floorplan

2
2
1
1
4
3
4
3
20 wafers needed for 40 copies
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Given n dice Di (i1n),
reticle size Find placement
of dice within the reticle and a
dicing plan To Minimize w, the
number of wafers used
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• Sort dice according to height

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• Sort dice according to height

• For all possible shelf widths, insert the dice
  into the shelves

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• Sort dice according to height

• For all possible shelf widths, insert the dice
  into the shelves

• Shift the dice to align them with the dice on
  other shelves and calculate z using IASA

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• Sort dice according to height

• For all possible shelf widths, insert the dice
  into the shelves

• Shift the dice to align them with the dice on
  other shelves and calculate z using IASA

• Choose the placement with the max z

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Get a shelf packing floorplan as the initial
floorplan Calculate Objective Value (1-a)
area a(100-z) While (not converge and of
move lt Move_Limit) choose a uniform
random number r make a random move
according to r calculate d New Objective
Value - Old Objective value If (d lt0)
Accept the move Else
Accept the move with probability exp(- (d/T))
Tß T
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Introduction to Multi-Project Wafer
Design flow
Side-to-side wafer dicing problem
Reticle floorplanning and wafer dicing problem
Experimental results
Conclusions and future research directions
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• GTMuch is a commercial tool for MPW
• Improve wafer yield z by 37.7 compared with
  GTMuch
• Improve wafer yield z by 30.5 compared with
  shelfshift

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GTMuch
Parquet
Simulated annealing
Shelfshift
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Introduction to Multi-Project Wafer
Design flow
Side-to-side wafer dicing problem
Reticle floorplanning and wafer dicing problem
Experimental results
Conclusions and future research directions
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We presented a MPW design flow
We propose practical mathematical programming
formulations and efficient heuristics, which can
be extended to the case when margins are allowed
The shelf packing and shifting algorithm can
improve yield by 37.7 while reducing reticle
area by 3.3 compared to GTMuch.
By using the simulated annealing code, we can
further improve wafer-dicing yield by 30.5 at
the expense of an increase of area by 3.3.
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Validate proposed methods on industry testcases
Extend the proposed algorithms to round wafer
Multiple dicing plans
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