Processing Rate Optimization by Sequential System Floorplanning - PowerPoint PPT Presentation
Title:
Processing Rate Optimization by Sequential System Floorplanning
Description:
For a wire e, w(e) is the number of flip-flops on it and d(e) is the delay of it. ... Exactly one flip-flop on each net. Wire delays are computed as Manhattan ... – PowerPoint PPT presentation
Number of Views:47
Avg rating:3.0/5.0
Title: Processing Rate Optimization by Sequential System Floorplanning
1
Processing Rate Optimization by Sequential
System Floorplanning
- Jia Wang1, Ping-Chih Wu2, and Hai Zhou1
- 1Electrical Engineering Computer Science
- Northwestern University, U.S.A
- 2Cadence Design Systems Inc, U.S.A
2
Motivation
- Optimize the performance of a sequential system.
- Optimize the frequency (clock period).
- Minimal period retiming. (4 Lin et al.
ICCAD
