Software To Design Next-gen Silicon Chips (Prof. Markov)

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Software To Design Next-gen Silicon Chips (Prof.
Markov)

• Difficult manufacturing (2-3B per
  fab),expensive masks (1M per mask set)
• FPGAs allow amortizing the cost,but with a
  significant performance loss
• Recently-discovered compromisestructured ASICs
• Our S/W is used in the LSI Logics tool-chainfor
  the RapidChip architecture (successful
  customers HP, SGI, CISCO, Nortel Networks,
  Raytheon, Seagate, 3COM, Alcatel,Hitachi,
  Fujitsu, IP Wireless, Cryptek)

S/W for Chip Floorplanning
Contact email imarkov_at_eecs.umich.edu