SBC6713e

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SBC6713e

• DSP based SBC for embedded applications

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SBC6713E Block Diagram
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SBC6713e Features
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Ethernet Coprocessor Core

• Network or internet communications
• Co-processor is responsible for Ethernet port
  protocol and data flow
• Dedicated processor provides always on
  connection that is easier to use
• Capable of supporting continuous 100 Mbps data
  flow to/from the DSP
• TCP/IP runs on DM640
• Leaves the 6713 completely free for applications
• Consumes 30 of the DM640

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SBC6713e DSP Core

• 6713 DSP running at 225MHz
• EMIF A is 75MHz
• 128MB SDRAM
• Interrupt control is in FPGA
• Edge/level control
• Software selected sources
• DMA transfer counting supports interrupts for
  block movements
• Two McBSP ports on DSP
• Mapped to FPGA and application headers

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Ethernet Data Flow
6713 HPI
10/100 Ethernet
DM640
PHY
128MBSDRAM
8MB SDRAM
32MB FLASH

• Ethernet data traffic is managed by the DM640
• The DM640 performs TCP/IP and data buffering
• HPI is used to move data to/from the 6713
• Efficient method reduces the burden on the 6713
• Only data for the 6713 is moved no extra
  traffic

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Booting the SBC6713e

• Steps in the boot process
• The DM640 boots from FLASH
• The DM640 loads the Spartan2E logic image
• The DM640 loads the 6713 over HPI with an
  application program
• Subsequent to boot, the DM640 acts the Ethernet
  host to the 6713
• Manages Ethernet traffic
• May reset the 6713
• May load new applications
• May load new logic images

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SBC6713e Peripherals

• Digital IO
• 32 bits of digital IO configurable by byte as
  input or output
• ESD and overvoltage protected
• UART
• RS232 port
• 1200 to 56K BAUD
• Fixed format 8 data, no stop, 1 parity
• 16 byte FIFOs in each direction
• Flow controls CTS, RTS based on FIFO levels
• Implemented in the FPGA

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SBC6713e Timebases

• DDS
• 0 to 25 MHz with 0.01Hz resolution
• Post-scaling to reduce jitter
• AD9851, same as on SBC6711
• DSP Timers
• 2x, 32 bit
• Clocked at DSP core rate, or by SW selected
  source
• SyncLink, ClockLink
• Clocks may be transmitted or received for
  multi-card systems
• External clock and interrupt SMB inputs

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Omnibus Modules

• SBC6713e supports all Omnibus Modules
• Omnibus clock is 37.5 MHz
• Fastest available (same as SBC6711)
• Data rate to gt70MB/s

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SBC6713e Logic

• Xilinx Spartan2E is core logic device
• Customizable logic is offered on this product
• Two offerings planned
• Standard product is closed design
• Open Logic Product is available with up to 600K
  gates
• Open Logic product provides logic source for DSP
  interface and most cores.
• VHDL source
• Test benches and simulations provided
• Existing logic consumes 17 of 600K gate part

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SBC6713e Release Schedule

• Hardware in house 3/15/04
• Pre-release 5/07/04
• Production Release 6/01/04
• Datasheets available soon