CSE 477' VLSI Systems Design

1
EE-354
Integrated Circuit Technology
History of Integrated Circuit Technology (Part
3)
Based on Course by Mary Irwin, Pennsylvania State
University

2
Historical Dates of IC Technology

• Transistor Bardeen et al. (Bell Labs) in 1947
• Bipolar transistor Schockley et al. in 1949
• First bipolar digital logic gate Harris in 1956
• First monolithic IC Jack Kilby in 1959
• First commercial IC logic gates Fairchild 1960
• TTL Circuits 1962 into the 1990s
• ECL Circuits 1974 into the 1980s

3
MOS Technology Dates

• MOSFET transistor - Lilienfeld (Canada) in 1925
  and Heil (England) in 1935
• CMOS Invented in 1960s, but plagued with
  manufacturing problems for 20 years.
• PMOS Limited use in calculators in 1960s
• NMOS Limited use in special applications in
  1970s
• CMOS in 1980s Contamination problems solved
  and CMOS became IC standard technology except for
  high speed.
• 1999 - BiCMOS, Silicon-Germanium, Stressed
  Silicon
• 2000 IBM SOI, Copper Wiring, Low-k Dielectrics

4
Moores Law

• In 1965, Gordon Moore predicted that the number
  of transistors that can be integrated on a die
  would double every 18 to 14 months (i.e., grow
  exponentially with time).
• Amazingly visionary million transistor/chip
  barrier was crossed in the 1980s.
• 2300 transistors, 1 MHz clock (Intel 4004) - 1971
• 16 Million transistors (Ultra Sparc III)
• 42 Million, 2 GHz clock (Intel P4) - 2001
• 140 Million transistor (HP PA-8500)

5
Intel 4004 Microprocessor
1971 1 MHz, 5V 5k Components
6
Intel Pentium (III) Microprocessor
1994 100 MHz, 3.3V 3M Components
7
Pentium III Layout
8
Intel Pentium (IV) Microprocessor
1999 1.2 GHz, 1.8V 42M Components
9
State-of-the Art Lead Microprocessors
10
Moores Law in Microprocessors
Transistors on lead microprocessors double every
2 years
Courtesy, Intel
11
Evolution in DRAM Chip Capacity
4X growth every 3 years!
0.07 ?m
0.1 ?m
0.13 ?m
0.18-0.25 ?m
0.35-0.4 ?m
0.5-0.6 ?m
0.7-0.8 ?m
1.0-1.2 ?m
1.6-2.4 ?m
12
Die Size Growth
Die size grows by 14 to satisfy Moores Law
Courtesy, Intel
13
Clock Frequency
Lead microprocessors frequency doubles every 2
years
10000
2X every 2 years
1000
P6
100
Pentium proc
486
Frequency (Mhz)
386
10
8085
286
8086
8080
1
8008
4004
0.1
1970
1980
1990
2000
2010
Year
Courtesy, Intel
14
Power Dissipation
Lead Microprocessors power continues to increase
100
Mainframe Chips (liquid cooled)
P6
Pentium proc
10
486
286
8086
Power (Watts)
386
8085
1
8080
8008
4004
0.1
1971
1974
1978
1985
1992
2000
Year
Power Removal is Immediate Problem (2003)
Courtesy, Intel
15
Power Density
Power density too high to keep junctions at low
temp
Courtesy, Intel
16
Design Productivity Trends
100,000
Logic Tr./Chip
(M)
10,000
Tr./Staff Month.
1,000
58/Yr. compounded
100
Complexity
Productivity (K) Trans./Staff - Mo.
Complexity growth rate
Logic Transistor per Chip
10
x
x
1
21/Yr. compound
x
x
x
x
x
Productivity growth rate
x
0.1
0.01
Complexity outpaces design productivity
Courtesy, ITRS Roadmap
17
Technology Directions SIA Roadmap
For Cost-Performance MPU (L1 on-chip SRAM cache
32KB/1999 doubling every two years)
http//www.itrs.net/ntrs/publntrs.nsf
18
Will CMOS Scaling Continue ?

• Technology shrinks by 0.7 per generation
• With every generation can integrate 2x more
  functions on a chip chip cost does not increase
  significantly
• Cost of a function decreases by 2x
• But
• How to design chips with more and more functions?
• Design engineering population does not double
  every two years
• Hence, a need for more efficient design methods
• Exploit different levels of abstraction

19
Design Abstraction Levels
SYSTEM
MODULE

GATE
CIRCUIT
DEVICE
G
D
S
n
n
20
Not Only Microprocessors
CellPhone
Digital Cellular Market (Phones Shipped)
(data from Texas Instruments)
21
Challenges in Digital Design
µ DSM
µ 1/DSM
Macroscopic Issues Time-to-Market
Millions of Gates High-Level Abstractions
Reuse IP Portability Predictability
etc. and Theres a Lot of Them!

• Microscopic Problems
• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
• Everything Looks a Little Different

?
22
Major Design Challenges

• Microscopic issues
• ultra-high speeds
• power dissipation and supply rail drop
• growing importance of interconnect
• noise, crosstalk
• reliability, manufacturability
• clock distribution

• Macroscopic issues
• time-to-market
• design complexity (millions of gates)
• high levels of abstractions
• reuse and IP, portability
• systems on a chip (SoC)
• tool interoperability