VLSI Digital Systems Design

1
VLSI Digital Systems Design

• CMOS Processing

2
Si Purification

• Chemical purification of Si
• Zone refined
• Induction furnace
• Si ingot melted in localized zone
• Molten zone moved from one end to the other
• Impurities more soluble in melt than in solid
• Impurities swept to one end of ingot
• Pure Si intrinsic Si (impurities lt 1109)

3
Czochralski Technique forSingle-Crystal Ingot
Growth, Melt

• Remelt pure Si
• Si melting point 1412 C
• Quartz crucible with graphite liner
• RF induction heats graphite
• Dip small Si seed crystal into melt
• Seed determines crystal orientation

4
Czochralski Technique forSingle-Crystal Ingot
Growth, Freeze

• Withdraw seed slowly while rotating
• Withdrawal and rotational rates determine ingot
  diameter
• 30-180 mm/hour
• Largest current wafers 300 mm
• Si crystal structure diamond

5
Single-Crystal Ingot to Wafer

• Diamond saw cuts grown crystal into slices
  wafers
• 0.25-1.00 mm thick
• Polish one side of wafer to mirror finish

6
Oxidation Converts Si to SiO2

• Wet oxidation
• Oxidizing atmosphere contains water vapor
• 900-1000 C
• Rapid
• Dry oxidation
• Oxidizing atmosphere pure oxygen
• 1200 C
• Volume of SiO2 2 x volume of Si
• SiO2 layer grows above Si surface approximately
  as far as it extends below Si surface

7
Dopants

• Si is semiconductorRconductor lt RintrinsicSi lt
  Rinsulator
• Dopants impurity atoms
• Can vary conductivity by orders of magnitude
• Dopant atom displaces 14Si atom in crystal
• Each 14Si atom shares 4 electronswith its 4
  neighbors in the crystal lattice,to form
  chemical bond
• Group (column) IV-A of Periodic Table

8
Donor Atoms Provide Electrons

• Group V-A of Periodic Table
• Phosphorus, 15P, and Arsenic, 33As
• 5 electrons in outer shell, 1 more than needed
• Excess electron not held in bond is free to drift
• If concentration of donors gt acceptors,n-type Si

9
Acceptor Atoms Remove Electrons from Nearby Atoms

• Group III-A of Periodic Table
• Boron, 5B
• 3 electrons in outer shell, 1 less than needed
• Incomplete bond,accepting electron from nearby
  atom
• Movement of electron is effective flow of
  positive current in opposite direction
• If concentration of acceptors gt donors,p-type Si

10
Epitaxy

• Greek for arranged upon or upon-ordered
• Grow single-crystal layeron single-crystal
  substrate
• Homoepitaxy
• Layer and substrate are same material
• Heteroepitaxy
• Layer and substrate differ
• Elevate temperature of Si wafer surface
• Subject surface to source of dopant

11
Deposition and Ion Implantation

• Deposition
• Evaporate dopant onto Si wafer surface
• Thermal cycle
• Drives dopant from Si wafer surface into the bulk
• Ion Implantation
• Energize dopant atoms
• When they hit Si wafer surface,they travel below
  the surface

12
Diffusion

• At temperature gt 800 C
• Dopant diffuses from area of high concentration
  to area of low
• After applying dopant, keep temperature as low as
  possible in subsequent process steps

13
Common Dopant Mask Materials

• Photoresist
• Polysilicon (gate conductor)
• SiO2 Silicon dioxide (gate insulator)
• SiN Silicon nitride

14
Selective Diffusion Process

• Apply dopant mask materialto Si wafer surface
• Dopant mask pattern includes windows
• Apply dopant source
• Remove dopant mask material

15
Positive Resist Example

• Apply SiO2
• Apply photoresist
• PR acid resistant coating
• Pass UV light through reticle
• Polymerizes PR
• Remove polymerized areas with organic solvent
• Developer solution
• Etch exposed SiO2 areas

16
Lithography Pattern Storage, Technique 1

• Mask
• Two methods for making
• Electron beam exposure
• Laser beam scanning
• Parallel processing

17
Lithography Pattern Storage, Technique 2

• Direct Write
• Two writing schemes
• Raster scan
• Vector scan
• Pro
• No mask expense
• No mask delay
• Able to change pattern from die to die
• Con
• Slow
• Expensive

18
Lithography Pattern Transmission

• Four types of radiation to convey pattern to
  resist
• Light
• Visible
• Ultraviolet
• Ion
• X-ray (does not apply to direct write)
• Electron

19
Lithographic Printing

• Contact printing
• Proximity printing
• Projection printing
• Refraction projection printing
• Reflection projection printing
• Catadioptric projection printing

20
Contact and Proximity Printing

• Contact printing
• 0.05 atm lt pressure lt 0.30 atm
• Proximity printing
• 20 µm lt mask-wafer separation lt 50 µm
• Pro
• Low cost
• Mask lasts longer because no contact
• Con
• Inferior resolution

21
Projection Printing

• Projection printing
• Higher resolution than proximity printing
• Numerical Aperture
• It was once believed that a high NAis always
  better.
• If NA too low, can't achieve resolution
• If NA too high, can't achieve depth of field
• DOF lambda/(2 NA2)

22
Refraction Projection Printing

• High resolution
• To transmit deep UV, optical components are
• Fused silica
• Crystalline fluorides
• Lenses are fused silica
• Chromatic
• Source bandwidth must be narrow
• KrF laser

23
Reflection and Catadioptric Projection Printing

• Reflection projection printing
• Polychromatic, larger spectral bandwidth
• Catadioptric projection printing
• Combines reflecting and refracting components
• Larger spectral bandwidth
• More than one optical axis
• Aligning optical elements can be very difficult

24
Minimum Channel Lengthand Gate Insulator
ThicknessImprove Performance

• Ids Beta(Vgs Vt)2 / 2
• Beta MOS transistor gain factor (
  (mu)(epsilon) / tox )( W / L )
• mu channel carrier mobility
• epsilon gate insulator permittivity (SiO2)
• tox gate insulator thickness
• W / L channel dimensions

25
Silicon Gate Process, Steps 1 2

• Initial patterning SiO2 layer
• Called field oxide
• Thick layer
• Isolates individual transistors
• Thin SiO2 layer
• Called gate oxide
• Also called thinox
• 10 nm lt thin oxide lt 30 nm

26
Silicon Gate Process, Step 3

• Polysilicon layer
• Polycrystalline not single crystal
• Formed when Si deposited
• Has high R when undoped
• Used as high-R resistor in static memory
• Used as
• Short interconnect
• Gate electrode
• Most importantallows precise definition of
  source and drain electrodes
• Deposited undoped on gate insulator
• Then doped at same time as source and drain
  regions

27
Silicon Gate Process, Steps 4 5

• Exposed thin oxide, not covered by poly,etched
  away
• Wafer exposed to dopant sourceby deposition or
  ion-implantation
• Forms n-type region in p-type substrateor vice
  versa
• Source and drain created in shadow of gate
• Si gate process called self-aligned process
• Polysilicon doped, reducing its R

28
Silicon Gate Process, Final Steps

• SiO2 layer
• Contact holes etched
• Metal (Al, Cu) evaporated
• Interconnect etched
• Repeat for further interconnect layers

29
Parasitic MOS transistors

• Formed from
• Diffusion regions of unrelated transistors
• Act as parasitic source and drain
• Thick (tfox) field oxide between
  transistorsoverrun by metal or poly interconnect
• Act as parasitic gate insulator and
• parasitic gate electrode
• Raise threshold voltage of parasitic transistor
• Make tfox thick enough
• Add channel-stop diffusion between transistors

30
Four Main CMOS Processes

• n-well process
• p-well process
• Twin-tub process
• Silicon on insulator

31
n-well Process, n-Well Mask A

• Mask A defines n-well
• Also called n-tub
• Ion implantation produces shallower wells than
  deposition
• Deeper diffusion also spreads further laterally
• Shallower diffusion better for more
  closely-spaced structures

32
n-well Process, Active Mask B, Page 1

• Mask B defines thin oxide
• Called active mask, since includes
• Area of gate electrode
• Area of source and drain
• Also called thinox
• thin-oxide
• island
• mesa

33
n-well Process, Active Mask B, Page 2

• Thin layer of SiO2 grown
• Covered with SiN Silicon Nitride
• Relative permittivity of SiO2 3.9
• Relative permittivity of Si3N4 7.5
• Relative permittivity of comb. 6.0
• Used as mask for steps forchannel-stop mask C
  andfield oxide step D

34
n-well Process, Channel-Stop Mask C

• Channel-stop implant
• Raises threshold voltage of parasitic transistors
• Uses p-well mask complement of n-well Mask A
• Where no nMOS, dope p-substrate to be p

35
n-well Process, Field Oxide Step D

• Thick layer of SiO2 grown
• Grows where no SiN
• Grows where no mask B no active mask
• Called LOCOS LOCal Oxidation of Silicon

36
n-well Process, Birds Beak

• Just as dopant diffuses laterally as well as
  vertically
• Field oxide also grows laterally,underneath SiN
• Tapering shape called birds beak
• Causes active area to be smaller
• Reduces W
• Some techniques limit this effect
• SWAMI SideWAll Masked Isolation

37
n-well Process, Planarity

• Field oxide higher than gate oxide
• Conductor thins or breaks
• Problem called step coverage
• To fix,pre-etch field oxide areasby 0.5 field
  oxide depth

38
n-well Process, Vt Adjust,After Field Oxide Step
D

• Threshold voltage adjust
• Optional
• Uses n-well mask A
• 0.5 v lt Vtn lt 0.7 v
• -2.0 v lt Vtp lt -1.5 v
• Add a negatively charged layer at Si-SiO2
• Lowers channel
• Called buried channel device

39
n-well Process, Poly Mask E

• Mask E defines polysilicon
• Poly gate electrodeacts as mask for source
  drain regions
• Called self-aligned

40
n-well Process, n Mask F

• n mask defines active areas to be doped n
• If in p-substrate,n becomes nMOS transistor
• If in n-well,n becomes ohmic contact to n-well
• Also called select mask

41
n-well Process, LDD Step G

• LDD Lightly Doped Drain
• Shallow n-LDD implant
• Grow spacer oxide over poly gate
• Second, heavier n implant
• Spaced from edge of poly gate
• Remove spacer oxide from poly gate
• More resistant to hot-electron effects

42
n-well Process, p Mask H

• p diffusion
• Uses complement of n mask
• p mask defines active areas to be doped p
• If in n-well,p becomes pMOS transistor
• If in p-substrate,p becomes ohmic contact to
  p-substrate

43
n-well Process, SiO2,After p Mask H

• Entire chip covered with SiO2
• No need for LDD for pMOS
• pMOS less susceptible to to hot-electron
  effectsthan nMOS
• LDD Lightly Doped Drain

44
n-well Process, Contact Mask I

• Defines contact cuts in SiO2 layer
• Allows metal to contact
• Diffusion regions
• Poly gates

45
n-well Process, Metal Mask J

• Wire it up!
• n-well Process, Passivation Step
• Protects chip from contaminants
• Which can modify circuit behavior
• Etch openings to bond pads for IOs

46
p-Well Process

• Transistor in native substratehas better
  characteristics
• p-well process has better pMOS thann-well
  process
• nMOS have better gain (beta) than pMOS

47
Twin-Tub Process

• Separately optimized wells
• Balanced performance nMOS pMOS
• Start with epitaxial layer
• Protects against latchup
• Form n-well and p-well tubs

48
Silicon-on-Insulator Process

• Uses n-islands and p-islands of siliconon an
  insulator
• Sapphire
• SiO2
• No n-wells, no p-wells

49
SOI Process Advantages

• No n-wells, no p-wells
• Transistors can be closer together
• Higher density
• Lower parasitic substrate capacitance
• Faster operation
• No latchup
• No body effect
• Enhanced radiation tolerance