InputOutput

1
Input/Output

• I/O processing is typically 1/3 of OS code
• Goals
• Software architecture that can handle many
  different types of devices
• Preferably configurable while system is running
• Simple interface to the user

2
Architectural Overview
Application Programs
Basic File System
O/S
I/O Control
Devices
Hardware
3
Device Controllers

• Also called adapter
• Has set of status and control registers
• Write to control register causes device action
• Read from status register clears register
• Out Port, Reg In Reg, Port
• May have data-in and data-out buffers
• Used to put data into blocks
• Used for error checking
• Bus may be busy, so not always be possible to
  pass data directly from device to CPU
• Controllers with a single buffer can only read or
  write

4
Device Controllers

• Registers and buffers mapped to certain addresses
  on the bus (I/O ports identified by 8 or 16-bit
  port number)
• Monitor example
• Video RAM is buffer
• Controller reads from video RAM and controls beam
  to draw to monitor
• Controller causes electron gun to excite screen
  phosphors to get desired color
• After scanning a line, controller turns off gun
  for horizontal retrace to get to beginning of
  next line
• After a full vertical scan, controller turns off
  gun for vertical retrace to top left corner of
  screen

5
Device Controllers

• Controllers are often hard to program, though
  development environments are available with some
  devices
• Reasons
• Hardware cost is extremely important in the
  marketplace, so reduce cost by not focusing on
  ease of use
• Driver is written only once, so its ok that it
  is difficult to program
• Legacy hardware and I/O bus designs remain for a
  long time, making fresh starts hard

6
Issues with Device Controllers

• Types of CPU-to-device I/O commands
• Memory-mapped write commands as a bit pattern
  to memory location
• Separate I/O instructions sent to separate space
  of addresses (port numbers)
• Use separate instructions and map a large buffer
  into memory locations
• Method of CPU-device signaling
• Device (or DMA controller) interrupts CPU
• CPU polls device status registers (programmed
  I/O)
• Method of CPU-device data transfer
• Direct memory access (DMA) special DMA
  controller hardware moves data between device and
  memory and sends interrupt to CPU only when
  transfer is complete
• CPU executes move instructions (programmed I/O)

7
Accessing Devices Memory-Mapped

• 3 methods
• I/O ports
• Memory-mapped I/O
• Hybrid methods no address ever assigned to both
  memory and I/O device, so no ambiguities
• Memory-mapped I/O
• Program can write to I/O buffers in the same way
  as any other memory location
• Device driver can be written in C (or other
  higher-level language)
• Protection of I/O buffers in same manner as
  protected memory not in user space, use r/w
  protection bits
• Reading control registers (status of device) same
  as reading any other memory location
• Need to disable caching to memory-mapped I/O
• How does this work with bus?

8
Pentium Example

• Buses are hierarchically arranged from fast (to
  main memory) to slow ISA (Industry Standard
  Architecture) bus
• PCI (Peripheral Component Interconnect) bridge
  filters addresses
• If 640K to 1M reserved for devices, then PCI
  bridge filters those addreses and sends to PCI
  bus
• Disadvantage need to decide on boot-up which
  addresses to reserve for devices
• Devices connected by
• USB (Universal Serial Bus) for slow I/O
  devices such as keyboard and mouse
• SCSI (Small Computer System Interface) large
  bandwidth for high performance devices (fast
  disks, scanners)

9
Accessing Devices Programmed I/O

• No DMA
• CPU has to write/read one byte at a time between
  main memory and device
• Example
• CPU polls busy bit in status register
• CPU writes byte into data-out register
• CPU sets write bit in status register
• CPU sets command-ready bit in status register
• Controller sets busy bit
• Controller reads data-out register, writes byte
• Controller clears command-ready, error, and busy
  bits in status register
• Repeat for each byte
• This takes up a lot of CPU time solution is to
  have a separate unit do the transfer (DMA
  controller)

10
DMA Controller

• CPU gives info to DMA controller by writing to
  control registers of DMA device
• To transfer data, DMA controller uses
• spare bus cycles (cycle stealing from CPU)
• burst mode transfer many bytes and once and
  hold onto bus for longer
• DMA controller is minimal CPU that runs trivial
  I/O programs does programmed I/O on behalf of
  CPU so that CPU can do other work
• DMA controller can be shared among all I/O
  controllers or I/O controller can have built-in
  DMA capability
• Address given to DMA controller must be physical
  since it does not have access to MMU
• Disadvantage of DMA controller it is slow
  compared to CPU if CPU is fast and has lots of
  idle time, can use CPU for data transfer rather
  than DMA controller

11
DMA Operation

• CPU sets DMAs registers address where to
  read/write in main memory, count of number of
  bytes, read or write command
• DMA issues request to controller
• Write/read to memory
• Acknowledgement received from controller to DMA
  that read/write is done
• DMA decrements count of bytes, increments address
  by one byte to get address of next byte to
  read/write
• After data transfer is done, interrupt CPU to let
  it know that data is in memory or has been
  transferred to device

Repeat steps 2 5 as long as count gt 0
12
Programmed I/O vs. DMA

• Slow devices use programmed I/O
• Modems
• Terminals
• Printers
• Fast devices use DMA
• Disk
• Graphics
• Network

13
Interrupts

• CPU checks interrupts after every instruction
• On boot-up, OS installs addresses of interrupt
  handlers into interrupt vector
• Points to start of interrupt service procedure
• Location of interrupt vector hardwired or is a
  table in memory with address stored in CPU
  register
• Interrupt priority
• When interrupt is raised, priority is assigned to
  it
• Currently running process is paused (and
  interrupt service run) only if interrupt has
  higher priority that process

14
Pentium Interrupt Vector

• 0 divide error
• 1 debug exception
• 2 null interrupt
• 3 breakpoint
• 4 INTO-detected overflow
• 5 bound range exception
• 6 invalid opcode
• 7 device not available
• 8 double fault
• 9 coprocessor segment overrun
• 10 invalid task state segment
• 11 segment not present
• 12 stack fault
• 13 general protection
• 14 page fault
• 15 Intel reserved
• 16 floating point error
• 17 alignment check
• 18 machine check

15
Interrupts

• Devices know their interrupt vector index
• To service interrupt,
• CPU handshakes with device to learn
  device-specific index into interrupt vector
• CPU then executes handler
• ACK used to avoid race conditions when multiple
  interrupts are issued
• Exceptions handled similarly
• Issue How to save state before handling
  interrupt?
• Storing information in kernel stack will require
  cache and TLB invalidation (basically a context
  switch)
• Pipelined machines many instructions at various
  states of execution
• Which to let complete before interrupt is
  processed?
• Which to restart after interrupt handling is
  done?

16
Precise Interrupts

• Leaves machine in well-defined state
• 4 properties
• Program counter (PC) is saved in known place
• All instructions before PC have been fully
  executed
• No instruction beyond PC has been executed
• State of instruction referenced by PC is known
  (executed or not)
• Some OSes may have some precise interrupts and
  others imprecise. Why is this possible?
• Example Fatal program errors need not be
  precise since process will just be killed anyway
• In some systems, CPU has extremely complex logic
  to get precise interrupt
• Bigger chip, but faster