InputOutput Subsystem

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Input/Output Subsystem

• Lecture 4
• MSIT 123 Computer Architecture and Operating
  Systems

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Digital Computer Subsystems
Systembus
The (three, four, five, or) six main units of a
digital computer. Usually, the link unit (a
simple bus or a more elaborate network) is not
explicitly included in such diagrams.
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Input/Output Devices and Controllers
Some input, output, and two-way I/O devices.
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Simple Organization for Input/Output
Input/output via a single common bus.
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I/O Organization for Greater Performance
Input/output via intermediate and dedicated I/O
buses
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Keyboard and Mouse
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Keyboard Switches and Encoding
Two mechanical switch designs and the logical
layout of a hex keypad.
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Pointing Devices
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How a Mouse Works
Mechanical and simple optical mice.
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Visual Display Units
CRT display unit and image storage in frame
buffer.
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How Color CRT Displays Work
The RGB color scheme of modern CRT displays.
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Flat-Panel Displays
Passive and active LCD displays.
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Other Display Technologies
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Hard-Copy Input/Output Devices
Scanning mechanism for hard-copy input.
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Character Formation by Dot Matrices
Forming the letter D via dot matrices of
varying sizes.
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Simple Dot-Matrix Printer Mechanism
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Common Hard-Copy Output Devices
Ink-jet and laser printers.
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How Color Printers Work
Red
Green
The RGB scheme of color monitors is
additive various amounts of the three primary
colors are added to form a desired color
Blue
Absence of green
Cyan
Magenta
The CMY scheme of color printers is
subtractive various amounts of the three primary
colors are removed from white to form a desired
color To produce a more satisfactory shade of
black, the CMYK scheme is often used (K black)
Yellow
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Other Input/Output Devices
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Sensors and Actuators
Collecting info about the environment and other
conditions
? Light sensors (photocells) ? Temperature
sensors (contact and noncontact types) ? Pressure
sensors
Stepper motor principles of operation.
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Networking of Input/Output Devices
With network-enabled peripherals, I/O is done via
file transfers.
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Input/Output in Control and Embedded Systems
The structure of a closed-loop computer-based
control system.
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Input/Output Problems

• Wide variety of peripherals
• Delivering different amounts of data
• At different speeds
• In different formats
• All slower than CPU and RAM
• Need I/O modules

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Input/Output Module

• Interface to CPU and Memory
• Interface to one or more peripherals

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External Devices

• Human readable
• Screen, printer, keyboard
• Machine readable
• Monitoring and control
• Communication
• Modem
• Network Interface Card (NIC)

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I/O Module Function

• Control Timing
• CPU Communication
• Device Communication
• Data Buffering
• Error Detection

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I/O Steps

• CPU checks I/O module device status
• I/O module returns status
• If ready, CPU requests data transfer
• I/O module gets data from device
• I/O module transfers data to CPU
• Variations for output, DMA, etc.

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I/O Module Diagram
Systems Bus Interface
External Device Interface
External Device Interface Logic
Data
Data Register
Data Lines
Status
Status/Control Register
Control
Address Lines
Input Output Logic
External Device Interface Logic
Data
Data Lines
Status
Control
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I/O Module Decisions

• Hide or reveal device properties to CPU
• Support multiple or single device
• Control device functions or leave for CPU
• Also O/S decisions
• e.g. Unix treats everything it can as a file

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Input Output Techniques

• Programmed
• Interrupt driven
• Direct Memory Access (DMA)

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Programmed I/O

• CPU has direct control over I/O
• Sensing status
• Read/write commands
• Transferring data
• CPU waits for I/O module to complete operation
• Wastes CPU time

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Programmed I/O - detail

• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later

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I/O Commands

• CPU issues address
• Identifies module ( device if gt1 per module)
• CPU issues command
• Control - telling module what to do
• e.g. spin up disk
• Test - check status
• e.g. power? Error?
• Read/Write
• Module transfers data via buffer from/to device

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Addressing I/O Devices

• Under programmed I/O data transfer is very like
  memory access (CPU viewpoint)
• Each device given unique identifier
• CPU commands contain identifier (address)

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I/O Mapping

• Memory mapped I/O
• Devices and memory share an address space
• I/O looks just like memory read/write
• No special commands for I/O
• Large selection of memory access commands
  available
• Isolated I/O
• Separate address spaces
• Need I/O or memory select lines
• Special commands for I/O
• Limited set

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Interrupt Driven I/O

• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts when ready

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Interrupt Driven I/OBasic Operation

• CPU issues read command
• I/O module gets data from peripheral whilst CPU
  does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data

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Interrupt Handling
Upon detecting an interrupt signal, provided the
particular interrupt or interrupt class is not
masked, the CPU acknowledges the interrupt (so
that the device can deassert its request signal)
and begins executing an interrupt service
routine. 1. Save the CPU state and call the
interrupt service routine. 2. Disable all
interrupts. 3. Save minimal information about the
interrupt on the stack. 4. Enable interrupts (or
at least higher priority ones). 5. Identify cause
of interrupt and attend to the underlying
request. 6. Restore CPU state to what existed
before the last interrupt. 7. Return from
interrupt service routine. The capability to
handle nested interrupts is important in dealing
with multiple high-speed I/O devices.
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CPU Viewpoint

• Issue read command
• Do other work
• Check for interrupt at end of each instruction
  cycle
• If interrupted-
• Save context (registers)
• Process interrupt
• Fetch data store
• See Operating Systems notes

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Design Issues

• How do you identify the module issuing the
  interrupt?
• How do you deal with multiple interrupts?
• i.e. an interrupt handler being interrupted

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Identifying Interrupting Module (1)

• Different line for each module
• PC
• Limits number of devices
• Software poll
• CPU asks each module in turn
• Slow

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Identifying Interrupting Module (2)

• Daisy Chain or Hardware poll
• Interrupt Acknowledge sent down a chain
• Module responsible places vector on bus
• CPU uses vector to identify handler routine
• Bus Master
• Module must claim the bus before it can raise
  interrupt
• e.g. PCI SCSI

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Multiple Interrupts

• Each interrupt line has a priority
• Higher priority lines can interrupt lower
  priority lines
• If bus mastering only current master can interrupt

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Example - PC Bus

• 80x86 has one interrupt line
• 8086 based systems use one 8259A interrupt
  controller
• 8259A has 8 interrupt lines

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Sequence of Events

• 8259A accepts interrupts
• 8259A determines priority
• 8259A signals 8086 (raises INTR line)
• CPU Acknowledges
• 8259A puts correct vector on data bus
• CPU processes interrupt

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PC Interrupt Layout
8259A
8086
IRQ0
IRQ1
IRQ2
IRQ3
INTR
IRQ4
IRQ5
IRQ6
IRQ7
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ISA Bus Interrupt System

• ISA bus chains two 8259As together
• Link is via interrupt 2
• Gives 15 lines
• 16 lines less one for link
• IRQ 9 is used to re-route anything trying to use
  IRQ 2
• Backwards compatibility
• Incorporated in chip set

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ISA Interrupt Layout
(IRQ 2)
8259A
80x86
8259A
IRQ0
IRQ0 (8)
IRQ1
IRQ1 (9)
IRQ2
IRQ2 (10)
IRQ3
INTR
IRQ3 (11)
IRQ4
IRQ4 (12)
IRQ5
IRQ5 (13)
IRQ6
IRQ6 (14)
IRQ7
IRQ7 (15)
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Direct Memory Access

• Interrupt driven and programmed I/O require
  active CPU intervention
• Transfer rate is limited
• CPU is tied up
• DMA is the answer

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DMA Function

• Additional Module (hardware) on bus
• DMA controller takes over from CPU for I/O

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I/O Data Transfer and DMA
DMA controller shares the system or memory bus
with the CPU.
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DMA Operation

• CPU tells DMA controller-
• Read/Write
• Device address
• Starting address of memory block for data
• Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when finished

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DMA TransferCycle Stealing

• DMA controller takes over bus for a cycle
• Transfer of one word of data
• Not an interrupt
• CPU does not switch context
• CPU suspended just before it accesses bus
• i.e. before an operand or data fetch or a data
  write
• Slows down CPU but not as much as CPU doing
  transfer

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DMA Configurations (1)
DMA Controller
I/O Device
I/O Device
Main Memory
CPU

• Single Bus, Detached DMA controller
• Each transfer uses bus twice
• I/O to DMA then DMA to memory
• CPU is suspended twice

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DMA Configurations (2)
DMA Controller
Main Memory
DMA Controller
CPU
I/O Device
I/O Device
I/O Device

• Single Bus, Integrated DMA controller
• Controller may support gt1 device
• Each transfer uses bus once
• DMA to memory
• CPU is suspended once

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DMA Configurations (3)
DMA Controller
Main Memory
CPU
I/O Device
I/O Device
I/O Device
I/O Device

• Separate I/O Bus
• Bus supports all DMA enabled devices
• Each transfer uses bus once
• DMA to memory
• CPU is suspended once

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I/O Channels

• I/O devices getting more sophisticated
• e.g. 3D graphics cards
• CPU instructs I/O controller to do transfer
• I/O controller does entire transfer
• Improves speed
• Takes load off CPU
• Dedicated processor is faster