Classifying Instruction Set Architectures

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Classifying Instruction Set Architectures

• Stack
• Register- Register
• Register Memory
• Accumulator
• Memory Memory

2
Stack

• The code CAB
• Push A
• Push B
• Add
• Pop C

3
Accumulator

• The Code CAB
• Load A
• Add B
• Store C

4
Register-Memory

• The Code CAB
• Load R1,A
• Add R3,R1,B
• Store R3,C

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Load-Store/ Register-register

• Code CAB
• Load R1,A
• Load R2,B
• Add R3,R1,R2
• Store R3,C
• Virtually every new architecture design after
  1980 uses load-store register architecture!

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ANOTHER EXAMPLE (Prob 2.4)

• A B C
• B A C
• D A B
• Assumptions
• Op Code is 8 bit represented by O,
• Address is 16-bit represented by A.
• All registers and data is 32-bit.

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EXAMPLE Accumulator
Instruc Comments Size of Operand Code Bytes MemoryUsage Bytes
Load B accumulator ? B OA 3 4
Add C accumulator ? B C OA 3 4
Store A store B C in A OA 3 4
Add C accumulator ? A C OA 3 4
Store B store A C in B OA 3 4
Negate negate accumulator O 1
Add A accumulator ? B A OA 3 4
Store D store A B in D OA 3 4
Total 22 28
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Example Mem to Mem
Instruction Comments Size of Operand Code Bytes Memory Usage
add A, B, C MEMA MEMB MEMC OAAA 7 12
add B, A, C MEMB MEMA MEMC OAAA 7 12
sub D, A, B MEMD MEMA MEMB OAAA 7 12
Total 21 36
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Load-Store
Instruc Comments Size of Operand R Reg Field (4-bit) Code Bytes Memory Usage Bytes
LW R1, B R1 ? MEMB OAR 28bits 4 4
LW R2, C R2 ? MEMC OAR 28bits 4 4
ADD R3, R1, R2 R3 ? B C ORRR 20bits 3
SW A, R3 MEMA B C OAR 28bits 4 4
ADD R1, R3, R2 R1 ? A C ORRR 20bits 3
SW B, R1 MEMB A C OAR 28bits 4 4
SUB R4, R3, R1 R4 ? A B ORRR 20bits 3
SW D, R4 MEMD A B OAR 28bits 4 4
Total 29 20
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STACK
Instruc Comments Size of Operand Code Bytes Memory Usage Bytes
Push B push B onto stack OA 3 4
Push C push C onto stack OA 3 4
Add top lt- B C O 1
Pop A A B C OA 3 4
Push A push A onto stack OA 3 4
Push C push C onto stack OA 3 4
Add top lt- A C O 1
Pop B B A C OA 3 4
Push A push A onto stack OA 3 4
Push B push B onto stack OA 3 4
Sub top lt- A B O 1
Pop D D A B OA 3 4
Total 30 36
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Example Reg Mem (Intel ISA-32)
Instruction Comments Size of Operand R Reg Spec (1 Byte) Code Bytes Memory Usage Bytes
Mov ECX, DWORD PTR C Mov C to ECX OAR 6 4
ADD EBX, DWORD PTR B B BC OAR 6 4
Mov EDX, EBX Temp Save OR 2 0
Mov EAX,EBX A BC OR 2 0
Mov DWORD PTR A, EAX Save A OA 6 4
ADD EAX, ECX AC OA 2 0
Mov EBX,EAX B AC OA 2 0
Mov DWROD PTR B, EBX Save B OAR 6 4
SUB EDX, EBX D A - B OA 2 0
Mov DWORD PTR D, EDX Save D OAR 6 4
Total 40 20
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Conclusion
Architecture Instruction Memory Accesses (in bytes) Data Memory Accesses (In bytes) Total
Accumulator 22 28 50
Memory/Memory 21 36 57
Stack 30 36 66
Load/Store 29 20 49
Reg-Mem(Intel) 40 20 60
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Pros Cons
Type Instruction Encoding Code Generation of Clock Cycles/ Inst. Code Size
Register-register Fixed-length Simple Similar Large
Register-memory Variable Length Moderate Different Medium
Memory-memory Variable-length Complex Large variation Compact
Advantages Disadvantages
Source Louisiana state University, ece
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Addressing Modes
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Addressing Modes
16
Common memory addressing mode in SPEC89 on VAX
architecture
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Size of Displacement SPEC2000 FP
16-bit displacement covers 75 to 99
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Percentage of Displacement
35
30
25
20
15
10
5
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Number of Bits needed for Displacement
18
Use of Immediate Operand
19
Immediate Addressing Mode-Size of Immediate
Operand
45
16-bit Immediate covers 50 to 80 in SPEC2000
40
FP
35
Percentage of Immediate
30
25
20
15
Int
10
5
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Number of Bits needed for Immediate Operand
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Popular Instructions
RANK 80x86 (SPECint92) Total Executed
1 Load (Memory Read) 22
2 Conditional Branch 20
3 Compare 16
4 Store 12
5 Add 8
6 And 6
7 Sub 5
8 Reg-Reg Move 4
9 Call 1
10 Return 1
Total 96
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Instructions for Control Flow

• The Measurements of branch and jump behavior are
  fairly independent of other measurements and
  applications.
• Four types of control flow change
• Conditional branches
• Jumps
• Procedure calls
• Procedure returns

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Control flow instructions SPEC2000
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Flow control instructions PC Relative also
called Branches

• Destination is specified by supplying a
  displacement that is added to the Program Counter
  (PC) This type of flow control instructions are
  called PC-relative. This way code can run
  independent of where it is loaded this is called
  position independence

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Branch distances in terms of number of
instructions in SPEC
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Conditional branch options

• Conditional Code (CC) register
• E.g. 80x86,ARM etc.
• Tests special bit set by ALU operations
• Advantage
• Sometimes condition is set free
• Disadvantage
• CC is extra state. Condition codes constrain the
  ordering of instructions since they pass
  information from one instruction to a branch

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Conditional branch options

• Conditional Register
• E.g. Alpha, MIPS
• Tests arbitrary register with the result of a
  comparison
• Advantage
• Simple
• Disadvantage
• Uses up register

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Conditional branch options

• Compare and branch
• E.g. PA-RISC, VAX
• Compare is part of the branch. Often compare is
  limited to subset
• Advantage
• One instruction rather than two for a branch
• Disadvantage
• May be too much work per instruction for
  pipelined execution

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Control Register Indirect

• Implement returns and indirect jumps using a
  register when target address is not known at
  compile time.
• These register indirect jumps are important for
  other features
• Case or switch statements
• Virtual functions or methods
• High order functions
• Dynamically shared libraries

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Types of compares in conditional branching
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Encoding an instruction set