Encryption Transaction with 3DES

1
Encryption Transaction with 3DES

• Team W2
• Yervant Dermenjian (W21)Taewan Kim (W22)
• Evan Mengstab (W23)
• Xiaochun Zhu (W24)

Objective To implement a secure credit card
transaction using 3DES encryption using
Kerberos-style authentication.
Design Manager Rebecca Miller
Current Stage Floor Plan and Structural Verilog
02/26/2004
2
Current Status

• Design Proposal (100 done)
• Architecture Proposal (100 done)
• Size Estimate and Floor Plan (100 done)

• More Accurate Transistor Count

• Floor Plan

• Structural Verilog simulation debugging

• To be done

• Gate-level design

• Chip Layout

• Spice Simulation

3
Design Decisions

• Eliminated cipher registers by reusing text
  register
• Reduced size of KeySub register to only hold 1
  (current) key
• Implemented Barrel Shifter using logic, rather
  than an additional ROM

4
Revised Architecture
64-gt 56
Sh_e
32b input
e/d
wr_en
64b 21
56b
Enc_ShiftL
KeySub 56b Register
21 mux
21 mux
demux
PC (wiring)
Key Latch
56
32b
Dec_ShiftR
Sh_d
Sub_rnd
D1/D1
21 mux
key_in
32
64
R
IP-1 wiring
OUT ready
R_L
21 mux
L
21 demux
PC-2 Wiring 56-gt48
ready
txt_in
Expand 32-gt48 wiring
32
48
Text 64b Register
IP wiring
21 mux
64
32
L
P 48-gt32 wiring
48
S-Box 512 x 4b
R
32
32
5
I/O Pins

• Required Inputs

• 32 bits data input at pins

• 1 bit reset at pin

• 1 bit encryption/decryption mode control at pin

• 1 bit clock at pin

• Provided Output

• 32 bits data output at pins

• 1 bit ready at pin
• 1 bit givekey at pin

6
Updated Transistor Counts and Area
7
Updated Transistor Counts and Area
8
Updated Transistor Counts and Area
9
Updated Transistor Counts and Area
10
Updated Transistor Counts and Area
Old Transistor Count New Transistor Count
Setup N/A 2,672
Key Scheduler 3,345 2,184
Encryption 10,484 5,616
Program Control N/A 1,409
Total 13,829 11,881
11
Floorplan
Output
64b 21 mux
Input
PC (wiring) 64 -gt 56
64b 21 demux
377.44 um
56b 21 mux
KeySub 56b Register
56b 21 mux
56b 21 mux
56b Key Latch
PC-2 wiring 56b -gt 48b
Des_ShiftR
Enc_ShiftL
Density .09 Trans/um2
S-box 512 x 4b
Program Control (Instruction ROM)
48b XOR
IP (wiring)
Expand
64b 21 mux
32b 21 demux
Text 64b Reg
125,534 um2 .126 mm2
32b XOR
P Wiring
334.37 um
12
Metal Usage
M2
M4
Metal 1 Horizontal local routing, Vdd,
Gnd Metal 2 Vertical local routing, Vdd,
Gnd Metal 3 Horizontal global routing, Clk,
Rst Metal 4 Vertical global routing, Clk, Rst
M1
M3
13
Structural Verilog
module crp(P, R, K_sub) output 132 P input
132 R input 148 K_sub wire 148
E wire 148 X wire 132 S assign E148
R32, R1, R2, R3, R4, R5, R4,
R5, R6, R7, R8, R9, R8, R9,
R10, R11, R12, R13, R12, R13,
R14, R15, R16, R17, R16, R17,
R18, R19, R20, R21, R20, R21,
R22, R23, R24, R25, R24, R25,
R26, R27, R28, R29, R28,
R29, R30, R31, R32, R1 // assign
X E K_sub xor(X1, E1,
K_sub1) xor(X2, E2, K_sub2) xor(X3,
E3, K_sub3) xor(X4, E4,
K_sub4) xor(X5, E5, K_sub5) xor(X6,
E6, K_sub6) xor(X7, E7,
K_sub7) xor(X8, E8, K_sub8) xor(X9,
E9, K_sub9) xor(X10, E10,
K_sub10) xor(X11, E11, K_sub11) xor(X12
, E12, K_sub12) sbox1 u0(
.addr(X0106), .dout(S0104) ) sbox2 u1(
.addr(X0712), .dout(S0508) ) sbox3 u2(
.addr(X1318), .dout(S0912) ) sbox4 u3(
.addr(X1924), .dout(S1316) ) sbox5 u4(
.addr(X2530), .dout(S1720) ) sbox6 u5(
.addr(X3136), .dout(S2124) ) sbox7 u6(
.addr(X3742), .dout(S2528) ) sbox8 u7(
.addr(X4348), .dout(S2932) ) assign
P132 S16, S7, S20, S21, S29,
S12, S28, S17, S1, S15, S23,
S26, S5, S18, S31, S10, S2, S8,
S24, S14, S32, S27, S3, S9, S19,
S13, S30, S6, S22, S11, S4,
S25 endmodule
14
Problems and Questions

• Permutation implemented by wiring may cause the
  wires to cross each other haphazardly. Is there
  any better way to implement this ?
• Can we find a way to reduce the instruction set
  to loop one DES cycle?