EE241 Project Presentation

1
EE241 Project Presentation

• Energy-Delay Tradeoff in Low Power, High Speed
  Digital Processors
• Nathan Chan
• Richard Lu
• Danijela Cabric

2
Motivation

• Low power design goal
• Minimize the energy consumption under throughput
  constraints
• Minimum delay achieved through
• Sizing (Logical Effort)
• Energy savings achieved through
• Multiple VDD, multiple VTH, sizing
• Energy-delay trade-off
• How much energy can we save if we allow
  certain delay penalty?

3
Questions To Be Asked

• Is it me, or does this laptop seem to be cooking
  my lap?

• Is Microsoft Word going to help me churn out the
  final report faster on a 2GHz machine versus a
  350MHz one?

• Can I slow things down, type up my paper without
  cooking my lap?

4
Outline

• Danijela Dual Vdd Option
• Richard Transistor Sizing
• Nathan Design Example
• Concluding Remarks, Future Work, Etc..

5
Inverter Chain

• Five stage inverter chain with FO4
• Optimally sized for the minimum delay using LE
• Energy distribution grows geometrically
• What is more effective sizing or dual VDD or
  both?

6
Inverter Dual VDD

• 10 Delay inc. for 55 Energy savings!
• VDDL as low as 0.8V
• Energy savings saturates at 60
• Last 2 stages consume the most energy

7
Memory Decoder (256)

• Optimally sized for the minimum delay using
  LE
• Total capacitance grows geometrically
• Number of active paths decrease
  geometrically
• Large wire load to the word driver
• Energy peak at the output of the predecoder!

8
Decoder Dual VDD

• Energy savings less than 30 for 10 delay
  increase
• VDDL as low as 0.8 V
• Saturates slower than inverter
• Peak energy at 5th stage ? apply VDDL up to
  4th stage

9
Dual VDD Comparison
10
Inverter Sizing
Constant Fan-out
Downsizing only last stage

• Beginning stages have negligible energy
  consumption
• Peak energy consumption occurs in the final
  stages
• Fixed load capacitance limits energy savings

11
Decoder Sizing

• Peak energy consumption per stage occurs in the
  middle of the path
• Transistor downsizing reduces peak energy
  consumption

12
Comparison

• Memory decoder is capable of achieving 30
  40 energy savings
• Inverter chain is capable of achieving 20
  25
• Whats the bottom line?
• If the peak energy consumption occurs in in
  the middle of the structure, transistor
  downsizing is effective.
• If peak energy consumption occurs at the end
  of the structure, sizing is not as
  effective as supply reduction.

13
Kogge-Stone Tree Adder

• 8-bit with mirrored gates
• reconvergent paths
• how do we size this thing?
• what does the energy profile look like?

14
Energy Profile (64-bit)
We can look at each stage, and each
bitslice Reference V. Stojanovic, D. Markovic,
B. Nikolic, M. Horowitz, R. Brodersen Energy-Dela
y Tradeoffs in Combinational Logic using Gate
Sizing and Supply Voltage Optimization
Energy is not increasing per stage. ? There are
energy peaks
So how does this hold for a smaller design?
15
Energy Profile (8-bit)
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Attacking the Energy Peaks
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Tradeoff
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Conclusion

• Validated claims in reference paper by
  Stojanovic, Markovic, Nikolic, etc..
• For increasing energy stages, supply optimization
  is a good idea, and sizing is secondary.
• For paths with internal energy peaks, dual
  supplies works and sizing is promising (SRAM).
• KS Adder may not be limited to just 30-35
  energy savings. Should try sizing next time.