Xilinx FPGA

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Xilinx FPGA

• Anselmo Lastra

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Topics

• FPGA internals
• Clock management
• Chipscope
• State Machines
• Design
• What if we were using a font thats 10 high, but
  2 of the rows are always blank?
• How about a given number of fixed-size sprites
  anywhere on the screen?

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Xilinx FPGA Internals
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Spartan2

• 4K bit RAM blocks
• Large amt of logic
• Program stored in SRAM

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Switch Matrix
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Pass Transistor
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Mux Controlled by Memory
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Logic Lookup Table

• Instead of gates
• So doesnt matter much how you specify your logic
• Ends up truth table

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Xilinx CLB
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Spartan 2

• At right two logic cells (LC)
• Two (four LCs) in CLB
• LUT is small RAM
• Can be used as RAM

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CLB

• Muxes can make full 6-input function
• Can generate some functions w/ up to 19 inputs
• Each LC can be 1 bit of an adder

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Xilinx IOB
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Spartan 2 IOB
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RAM

• Ours has 10 blocks for a total of 40Kbits SRAM

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Delay Lock Loops

• Circuitry to
• Synchronize internal clock to external clock
• Divide the clock
• Instead of how you were counting it
• Run the clock over low skew lines
• Double the clock frequency
• There are four on our chips

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Clock Synchronization

• Set internal to one cycle behind external
• Effectively clock edges are aligned

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Clock Division and Sync

• //synthesis attribute CLKDV_DIVIDE of dll is 8
• //synopsys translate_off
• defparam dll.CLKDV_DIVIDE 8
• //synopsys translate_on
• CLKDLL dll (.CLKIN(CLKIN), .CLKFB(CLK0),
  .RST(RESET), .CLK0(CLK0), .CLK90(), .CLK180(),
  .CLK270(), .CLK2X(), .CLKDV(DIV),
  .LOCKED(LOCKED))
• ----------
• CLKIn is input clock
• CLK0 is locked (indicated by LOCKED)
• DIV is divided by the CLKDV_DIVIDE factor

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Clock Division Example

• Here was set to divide-by-4

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Practical Matters

• Have found that clock DLL divisor only works
  reliably if you initialize it with reset

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Our Device Specs

• See http//direct.xilinx.com/bvdocs/publications/d
  s001_2.pdf

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Spartan 3
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Virtex-II
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Virtex-II Pro
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Links

• Link page on course web
• Hardware documentation
• Application notes on Xilinx web page
• Info on DLL
• http//www.xilinx.com/bvdocs/appnotes/xapp174.pdf
• http//www.xilinx.com/bvdocs/appnotes/xapp132.pdf

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Next

• Chipscope
• State Machines
• Design
• What if we were using a font thats 10 high, but
  2 of the rows are always blank?
• How about a given number of fixed-size sprites
  anywhere on the screen?