9 MSI Logic Circuits

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9 MSI Logic Circuits
Some of digital system operations Decoding and
encoding multiplexing demultiplexing
comparison code converting data busing. We will
study some ICs in MSI(medium-scale-integration)
category which can provide such operations.
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9-1 Decoders
A decoder accepts a set of inputs that represents
a binary number and activates only the output
that corresponds to that input number.
FIGURE 9-2 3-line-to-8-line (or 1-of-8)
decoder.
FIGURE 9-1 General decoder diagram.
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9-1 Decoders cont.
FIGURE 9-3 (a) Logic diagram for the 74ALS138
decoder (b) truth table (c) logic symbol.
(Courtesy of Fairchild, a Schlumberger company)
Some decoders have one or more ENABLE inputs used
to control the operation of the decoder.
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9-1 Decoders cont.
FIGURE 9-5 (a) Logic diagram for the 7442
BCD-to-decimal decoder (b) logic symbol (c)
truth table. (Courtesy of Fairchild, a
Schlumberger company)
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9-1 Decoders cont.
FIGURE 9-6 Example 9-3 counter/decoder
combination used to provide timing and sequencing
operations.
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9-2 BCD-TO-7-Segment Decoder/Drivers
FIGURE 9-7 (a) 7-segment arrangement (b)
active segments for each digit.
FIGURE 9-8 (a) BCD-to-7-segment decoder/driver
driving a common-anode 7-segment LED display (b)
segment patterns for all possible input codes.
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9-3 Liquid-Crystal Displays
FIGURE 9-9 Liquid-crystal display (a) basic
arrangement (b) applying a voltage between the
segment and the backplane turns ON the segment.
Zero voltage turns the segment OFF.
FIGURE 9-10 (a) Method for driving an LCD
segment (b) driving a 7-segment display.
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9-4 Encoder
FIGURE 9-12 General encoder diagram.
FIGURE 9-13 Logic circuit for an
octal-to-binary (8-line-to-3-line) encoder. For
proper operation, only one input should be active
at one time.
Question Determine the outputs of the encoder
when A3 and A5 are simultaneously high.
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9-4 Encoder cont.
A priority encoder includes the necessary logic
to ensure that when two or more inputs are
activated, the output code will correspond to the
highest-numbered input.
FIGURE 9-14 74147 decimal-to-BCD priority
encoder.
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9-4 Encoder cont.Switch Encoder
FIGURE 9-15 Decimal-to-BCD switch encoder.
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9-5 Troubleshooting
Observation/analysis is used to narrow the
location of the fault to a small area of the
circuits. Divide-and-conquer is used to identify
the location of the problem after
observation/analysis has generated a number of
possibilities.
FIGURE 9-4 Four 74AS138s forming a 1-of-32
decoder.
Example 9-7 A technician tests the circuit of
Figure 9-4 by using a set of switches to apply
the input code at A4 through A0. She observes
that all of the odd-numbered outputs respond
correctly, but all of the even-numbered outputs
fail to respond when their code is applied.
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9-5 Troubleshooting cont.

• Solution The most probable faults would be those
  that prevent A0 from going LOW. These include
• A fault switch connected to A0
• A break in the path between the switch and the A0
  line
• An external short from the A0 line to VCC
• An internal short to VCC at the A0 inputs of
  any one of the decoder chips
• The left hand circuit is used to identify the
  cause.

FIGURE 9-17 Troubleshooting circuitry in
Example 9-7.
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9-6 Multiplexers (Data Selector)
FIGURE 9-18 Functional diagram of a digital
multiplexer (MUX).
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9-6 Multiplexers cont.
FIGURE 9-20 Four-input multiplexer
FIGURE 9-21 (a) Logic diagram for the 74ALS151
multiplexer (b) truth table (c) logic symbol.
(Courtesy of Fairchild, a Schlumberger company)
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9-6 Multiplexers cont.
FIGURE 9-22 Example 9-9 two 74HC151s combined
to form a 16-input multiplexer.
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9-7 Multiplexer Applications
Data Routing
FIGURE 9-24 System for displaying two
multidigit BCD counters one at a time.
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9-7 Multiplexer Applications cont.
Parallel-to-Serial Conversion
FIGURE 9-25 (a) Parallel-to-serial converter
(b) waveforms for X7X6X5X4X3X2X1X0 10110101.
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9-7 Multiplexer Applications cont.
Operation Sequencing
FIGURE 9-26 Seven-step control sequencer.
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9-7 Multiplexer Applications cont.
Logical Function Generation
FIGURE 9-27 Multiplexer used to implement a
logic function described by the truth table.
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9-8 Demultiplexers (Data Distributors)
A DEMUX takes a single input and distributes it
over several outputs.
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9-8 Demultiplexers (Data Distributors) cont.
FIGURE 9-29 1-line-to-8-line demultiplexer.
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9-8 Demultiplexers (Data Distributors) cont.
FIGURE 9-30 (a) The 74ALS138 decoder can
function as a demultiplexer with E1 used as the
data input. (b) Typical waveforms for a select
code of A2 A 1 A 0 000 show that O0 is
identical to the data input I on E1.
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9-8 Demultiplexers (Data Distributors) cont.
FIGURE 9-32 Security monitoring system.
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9-8 Demultiplexers (Data Distributors) cont.
FIGURE 9-33 Synchronous data transmission
system that is used to serially transmit four
four-bit data words from a transmitter to a
remote receiver.
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9-8 Demultiplexers (Data Distributors) cont.
FIGURE 9-34 Waveforms during one complete
transmission cycle.
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9-9 More Troubleshooting
Example 9-14 Suppose that the synchronous data
transmission system of Figure 9-33 is
malfunctioning as follows the Z waveform is
correct, but the O0 waveform is identical to the
Z waveform at all times while the other outputs
are constantly LOW. Assume that the receiver
circuit is soldered on a PC board with no IC
sockets.

• Solution Observation/analysis should be used to
  determine the possible causes. Divide-and-conquer
  should be used to isolate the problem. The most
  obvious cause appears to be that S and S of the
  DEMUX are always LOW as data are transmitted.
  Assuming that this is true, there are many
  possible causes for this symptom. Lets list
  them
• S0 of the MUX or Q0 of the word counter could be
  shorted to ground, preventing the counter from
  incrementing.
• The word counter could be defective(shorted or
  open CLK line, MR shorted to ground, or internal
  faults).
• The bit counter could be defective(shorted or
  open CLK line or Q1, MR shorted to ground, or
  internal faults).
• The INVERTER or the AND gate could be defective
  (shorted or open outputs or inputs, or internal
  faults).
• FF Y could be defective (D, CLR, or Y shorted to
  ground, or internal faults).
• The one-short could be defective .
• The transmitted clock line may be open between
  the transmitter and the receiver.

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9-9 More Troubleshooting cont.
FIGURE 9-35 Example 9-14 a troubleshooting
tree diagram.
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9-10 Magnitude Comparators
FIGURE 9-36 Logic symbol and truth table for a
74HC85 (7485, 74LS85) four-bit magnitude
comparator.
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9-10 Magnitude Comparators cont.
FIGURE 9-37 (a) 74HC85 wired as a four-bit
comparator (b) two 74HC85s cascaded to perform
an eight-bit comparison.
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9-10 Magnitude Comparators cont.
FIGURE 9-38 Magnitude comparator used in a
digital thermostat.
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9-11 Code Converters
A code converter is a logic circuit that changes
data presented in one type of binary code to
another type of binary code.
FIGURE 9-39 Basic idea of a two-digit
BCD-to-binary converter.
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9-11 Code Converters
FIGURE 9-40 BCD-to-binary converter
implemented with 74HC83 four-bit parallel adders.
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9-12 Data Busing
FIGURE 9-41 Three different devices can
transmit eight-bit data over an eight-line data
bus to a microprocessor only one device at a
time is enabled so that bus contention is avoided.
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9-13 The 74LS173/HC173 Tristate Register
FIGURE 9-42 Truth table and logic diagram for
the 74ALS173 tristate register. (Courtesy of
Fairchild, a Schlumberger company)
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9-13 The 74LS173/HC173 Tristate Register
FIGURE 9-43 Logic symbol for the
74ALS173/HC173 IC.
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9-14 Data Bus Operation
FIGURE 9-44 Tristate registers connected to a
data bus.
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9-14 Data Bus Operation cont.
FIGURE 9-45 Signal activity during the
transfer of the data 1011 from register A to
register C.
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9-14 Data Bus Operation cont.
FIGURE 9-46 Simplified way to show signal
activity on data bus lines.
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9-14 Data Bus Operation cont.
Simplified Bus Representation
FIGURE 9-47 A 74HC541 octal bus driver
connects the outputs of an analog-to-digital
converter (ADC) to an eight-line data bus. The D0
output connects directly to the bus showing the
capacitive effects.
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9-14 Data Bus Operation cont.
FIGURE 9-48 Simplified representation of bus
arrangement.
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9-14 Data Bus Operation cont.
FIGURE 9-49 Bundle method for simplified
representation of data bus connections. The /8
denotes an eight-line data bus.
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9-14 Data Bus Operation cont.
FIGURE 9-50 Bidirectional register connected
to data bus.
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9-15 PLDs and Truth Table Entry
FIGURE 9-52 Three different ways to enter an
XOR truth table in CUPL.
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9-15 PLDs and Truth Table Entry cont.
FIGURE 9-53 An active-HIGH output 1-of-8
decoder using CUPL table entry format.
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9-15 PLDs and Truth Table Entry cont.
FIGURE 9-54 74LS138 decoder implemented on a
GAL 16V8.
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9-15 PLDs and Truth Table Entry cont.
FIGURE 9-55 A decimal-to-BCD priority encoder.