Bridging the gap between asynchronous design and designers

1
Bridging the gap between asynchronous designand
designers

• Part II
• Logic synthesis fromconcurrent specifications

2
Outline

• Overview of the synthesis flow
• Specification
• State graph and next-state functions
• State encoding
• Implementability conditions
• Review of some advanced topics

3
Book and synthesis tool

• J. Cortadella, M. Kishinevsky, A. Kondratyev,L.
  Lavagno and A. Yakovlev,Logic synthesis for
  asynchronouscontrollers and interfaces,Springer-
  Verlag, 2002
• petrifyhttp//www.lsi.upc.es/petrify

4
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
5
Specification
x
x
y
y
z
z
x-
z
x
y
z-
y-
Signal Transition Graph (STG) (Petri Net with
interpreted events (often free-choice))
6
Token flow
7
State graph
8
Next-state functions
9
Gate netlist
x
y
z
10
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
11
VME bus
12
STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
13
Choice Read and Write cycles
DSr
DSw
LDS
D
LDTACK
LDS
D
LDTACK
DTACK
D-
DSr-
DTACK
D-
DSw-
14
Choice Read and Write cycles
15
Circuit synthesis

• Goal
• Derive a hazard-free circuitunder a given delay
  model andmode of operation

16
Speed independence

• Delay model
• Unbounded gate / environment delays
• Certain wire delays shorter than certain paths in
  the circuit
• Conditions for implementability
• Consistency
• Complete State Coding
• Persistency

17
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
18
STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
19
Binary encoding of signals
DSr
DTACK-
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
D
D-
DSr-
DTACK
20
Binary encoding of signals
DSr
DTACK-
10000
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
10010
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
10110
01110
10110
D
D-
DSr-
DTACK
(DSr , DTACK , LDTACK , LDS , D)
21
Excitation / Quiescent Regions
22
Next-state function
0 ? 1
0 ? 0
1 ? 1
1 ? 0
23
Next-state function. Exercise
A
B
C
A-
B-
C-
24
Next-state function
0 ? 1
0 ? 0
1 ? 1
1 ? 0
25
Karnaugh map for LDS
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
26
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
27
Concurrency reduction
LDS
LDS-
LDS-
LDS-
10110
10110
28
Concurrency reduction
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
29
State encoding conflicts
LDS
LDTACK-
LDS-
LDTACK
10110
10110
30
Signal Insertion
LDTACK-
LDS
LDS-
LDTACK
101101
101100
D-
DSr-
31
Regions and excitation regions
a
a
enter
exit
non-cross
excitation region

• Region set of states r s.t. each event a
• either enters, or exits or does not cross it
  (Nielsen et el. 92)
• Pre-region a exits r
• Post-region a enters r
• Excitation region all states exited by a
• Any region is a union of minimal regions

32
Event insertion (Vanbekbergen 92)
a
b
c
delay exit transitions by x
ER(x)
SR(x)
b
S - ER(x)
a
x
x
x
x
b
c
ER(x)
S - ER(x)
33
Event insertion (Vanbekbergen 92)

• Properties to preserve during insertion
• trace equivalence
• speed-independence
• necessary and sufficient conditions
• persistency
• (Speed-Independence Preserving set)

• commutativity

a
b
b
a
34
Regions and SIP sets

• Legal SIP set
• region
• persistent excitation region
• exit border of persistent region
• intersection of pre-regions
• (if forward connected)

35
State signal insertion (Vanbekbergen 92)
S0
S0
x
x-
S-
S
S-
S
S1
S1

• S (ER(x)) and S- (ER(x-)) must be SIP
  (speed-independence)
• I-partition must not have illegal arcs
  (well-formedness)
• e.g. S0 è S1, S è S0, S1 è S are illegal

36
Using regions to find bipartitions

• Bricks
• minimal regions
• intersections of pre-regions and post-regions
• Blocks È bricks

(r1 Ç r2) È (r3 Ç r4)
37
From bipartition to I-partition
100
010
x
y
x
y
x
y
y-
x-
y-
x-
110
z-
y-
x-
y-
x-
111
y-
x-
y
x
y
x
011
101
y-
x-

• Find a bipartition b, b
• Find (by expansion) exit borders which are
• well-formed and SIP
• Add the new state signal z

001
z-
000
y
x
38
The cost function

• Comparison among pairs of I-partitions
• correctness (SIP, well-formed, ...)
• number of solved CSC conflicts
• estimation of logic
• Trade-off between CSC conflicts and estimated
  logic

39
Conclusions

• Regions guide the search among blocks of states
• Regions are the base of symbolic manipulations of
  TSs
• Property-preserving TS transformations
• Completeness
• all CSC conflicts are solvable for
  excitation-closed TSs
• Designer/tool interaction made easier by
• STG è TS è STG transformations
• Public domain PN and asynchronous circuit
  synthesis tool Petrify
• http//www.ac.upc.es/vlsi/petrify/petrify.html

40
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
41
Complex-gate implementation
42
Implementability conditions

• Boundedness (reachability space is finite)
• Consistency
• Rising and falling transitions of each signal
  alternate in any trace
• Complete state coding (CSC)
• Next-state functions correctly defined
• Persistency
• No event can be disabled by another event (unless
  they are both inputs)

43
Persistency
a
c
b
is this a pulse ?
Speed independence ? glitch-free output behavior
under any delay
44
Implementability conditions

• Bound Consistent CSC Persistent
• There exists a speed-independent circuit that
  implements the behavior of the STG(under the
  assumption that any Boolean function can be
  implemented with one complex gate)

45
Implementability analysis

• Boundedness (reachability graph with ? markings)
• Consistency (concurrency alternation)
• Polynomial for free-choice
• Persistency (conflicts)
• Polynomial for free-choice
• CSC (requires SG extraction)

Implementability analysis is not hard
46
Part3. Advanced topics

• Logic Decomposition
• Optimization based on timing information

47
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48
ER(d)
ER(d-)
49
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
Complex gate
50
Implementation with C elements
? S ? z ? S- ? R ? z- ? R- ?

• S (set) and R (reset) must be mutually exclusive
• S must cover ER(z) and must not intersect
  ER(z-) ? QR(z-)
• R must cover ER(z-) and must not intersect
  ER(z) ? QR(z)

51
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
S
d
C
R
52
but ...
S
d
C
R
53
Starting from state 0000 (R1 and S0)
a R- b a- c S d
S
d
C
R
54
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
Monotonic covers
55
C-based implementations
c
d
C
b
a
c
weak
c
d
weak
d
a
a
b
generalized C elements (gC)
56
Speed-independent implementations

• Implementability conditions
• Consistency
• Complete state coding
• Persistency
• Circuit architectures
• Complex (hazard-free) gates
• C elements with monotonic covers
• ...

57
Synthesis exercise
1011
0011
0111
Derive circuits for signals x and z (complex
gates and monotonic covers)
58
Synthesis exercise
1011
wx
yz
00
01
11
10
-
1
1
0
00
0011
-
1
1
0
01
-
0
0
0
11
-
1
1
0
10
0111
Signal x
59
Synthesis exercise
1011
wx
yz
00
01
11
10
-
0
0
0
00
0011
-
0
0
0
01
-
1
1
1
11
-
1
0
0
10
0111
Signal z
60
Logic decomposition example
61
Logic decomposition example
y-
1001
1011
z-
w-
1000
0001
w
y
x
w-
z-
1010
0000
0101
0011
w-
z-
y
x
0010
0100
x-
y
x
z
0110
0111
62
Logic decomposition example
s1
y-
s
1001
1011
z-
s-
w
1001
1000
z-
s-
y
w-
0011
0001
1000
1010
y
s-
x
w-
z-
x-
0000
0101
1010
w-
z-
y
x
0111
0010
0100
s
y
x
s0
z
0111
0110
63
Logic decomposition example
s1
y-
y-
1001
1011
z-
s-
s-
w
1001
1000
z-
s-
y
w-
z-
w-
w
0011
0001
1000
1010
y
s-
x
w-
z-
x-
0000
0101
1010
y
x
x-
w-
z-
y
x
0111
0010
0100
s
s
y
x
z
s0
z
0111
0110
64
Speed-independent Netlist
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
65
Adding timing assumptions
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
66
Adding timing assumptions
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
67
State space domain
DSr
LDTACK-
68
State space domain
DSr
LDTACK-
69
State space domain
DSr
LDTACK-
Two more unreachable states
70
Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
71
Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
-
0
0
1
-
-
One more DC vector for all signals
One state conflict is removed
72
Netlist with one constraint
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
73
Netlist with one constraint
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
74
Conclusions

• STGs have a high expressiveness power at a low
  level of granularity (similar to FSMs for
  synchronous systems)
• Synthesis from STGs can be fully automated
• Synthesis tools often suffer from the state
  explosion problem (symbolic techniques are used)
• The theory of logic synthesis from STGs can be
  found in

J. Cortadella, M. Kishinevsky, A. Kondratyev, L.
Lavagno and A. Yakovlev,Logic Synthesis of
Asynchronous Controllers and Interfaces,Springer
Verlag, 2002.
75
Synthesis from asynchronous HDL

• CSP based languages
• CSP communicating sequential processes T.
  Hoare
• Two synthesis techniques
• based on program transformations Caltech
• based on direct compilation Philips
• Complete shift in design methodology is required

76
Using CSP for control generation

• After li goes high do full handshake at the
  right, then complete handshake at the left and
  iterate.

ro
li
Q element
ri
lo
STG
li
ro
ri
ro-
ri-
lo
li-
lo-
liroriro-not rilonot lilo-
CSP

• sequencing operator
• ro ro goes high ro- ro goes low
• li wait until li is high not li wait
  until li is low

77
Using CSP for control generation
liroriro-not rilonot lilo-
CSP
weak
ri
Production rules li -gt ro ri -gt ro- not ri
-gt lo not li -gt lo-
ro
li

• Conflict ro and ro- are not mutually exclusive
• Eliminate conflict by state signal insertion (
  CSC)

78
Conflict elimination
lirorixxro-not rilonot
lix-not xlo-
CSP
Production rules not x and li -gt ro x or not
li -gt ro- x and not ri -gt lo not x or ri -gt
lo- ri -gt x not li -gt x-
ro
li
x
FF
not x
lo
ri
79
Conclusions

• Generating circuits from CSP control program is
  similar to STG synthesis
• One can be reduced to the other
• Particular technique may vary. Direct CSP program
  transformations can be (and were) used instead of
  methods based on state space generation
• See reference list for more details

80
Buffer example in Tangram
(a?byte b!byte) begin x0 var byte
forever do a?x0 b!x0 od end
a
b
Buffer
passive port
Each circle mapped to a netlist
active port

Q element
a
b
Data path
81
Summary

• Tangram program is partitioned into data path and
  control
• Data path is implemented as dual or single rail
• Control is mapped to composition of standard
  elements ( etc)
• Each standard element is mapped to a circuit
• Post-optimization is done
• Composing islands of control elements and
  re-synthesis with STG can give more aggressive
  optimization
• Philips made a few chips using Tangram, including
  a product 8051 micro-controller in low-power
  pager Muna (25 wks battery life from one AAA
  battery)
• Public domain Tangram compiler is available
  (Balsa, U. Manchester)

82
Burst mode FSM

• Close to synchronous FSMs with binary encoded I/O
• Work in bursts
• Input transitions fire
• Output transitions fire
• State signals change
• Mostly limited to fundamental mode next input
  burst cannot arrive before stabilization at the
  outputs

s1
b-/x-
ab/y
a-/xy-
s2
s4
c-/y
c/y-
s3
83
Extended Burst mode

• Directed dont cares (b) some concurrency is
  allowed for input transitions that do not
  influence an output burst
• Conditional guards ltbgt if b1 then

s1
b-/x-
ab/y
ltbgta-/xy-
s2
s4
c-/y
ltbgtc/y-
s3
84
Synthesis of XBM

• Next state and output functions free of
  functional and logic hazards
• Sequential feedbacks should not introduce new
  hazards
• State assignment
• one state of the BM spec to one layer of Karnaugh
  map
• compatible layers are merged
• layers are compatible if merging does not
  introduce CSC violations or hazards
• Layers are encoded using race free encoding

85
XBM and STG
x-
a
b
s1
b-/x-
ab/y
y
ltbgta-/xy-
s2
s4
c-/y
ltbgtc/y-
a-
c
s3
eps
y-
c-
y-
x
y
b-
86
Summary

• Specification XBM is subclass of STGs
• Synthesis techniques are extensions of
  synchronous state assignment and logic
  minimization
• Timing
• environment is limited to fundamental mode
  (difficult for pipelined and highly concurrent
  systems)
• internals are delay insensitive
• See reference list for details