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Midterm 3 Revision 2

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Basic logic. Boolean equations, truth tables. NOT, AND, OR, NAND, NOR, ... From Boolean expressions to logic gates. More than one way to map expressions to gates ... – PowerPoint PPT presentation

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Title: Midterm 3 Revision 2


1
Midterm 3 Revision 2
CS 147 Lecture 20
  • Prof. Sin-Min Lee
  • Department of Computer Science

2
Combinational logic
  • Digital system whose output behavior depends only
    on the current inputs
  • Basic logic
  • Boolean equations, truth tables
  • NOT, AND, OR, NAND, NOR, XOR, . . ., minimal set
  • Logic realization
  • two-level logic and canonical forms
  • Simplification
  • uniting theorem
  • grouping of terms in Boolean functions
  • Alternate representations of Boolean functions
  • cubes
  • Karnaugh maps

3
A simple example 1-bit binary adder
Cin
Cout
A A A A A
  • Inputs A, B, Carry-in
  • Outputs Sum, Carry-out

B B B B B
S S S S S
A B Cin Cout S 0 0 0 0 0 1
0 1 0 0 1 1 1 0 0 1 0 1 1 1 0
1 1 1
0 1 1 0 1 0 0 1
0 0 0 1 0 1 1 1
A
S
B
FA
Cout
Cin
S A B Cin A B Cin A B Cin A B Cin
Cout A B Cin A B Cin A B Cin A B Cin
4
Possible logic functions of two variables
  • There are 16 possible functions of 2 input
    variables
  • in general, there are 2(2n) functions of n
    inputs

X
F
Y
X Y 16 possible functions (F0F15)0 0 0 0 0
0 0 0 0 0 1 1 1 1 1 1 1 10 1 0 0 0 0 1 1 1 1 0 0
0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0
1
X
not X
Y
not Y
X xor Y
X Y
X and Y
X nand Y
X or Y
X nor Y
5
Minimal set of functions
  • Can we implement all logic functions from NOT,
    NOR, and NAND? yes
  • In fact, we can do it with only NOR or only NAND
  • NOT is just a NAND or a NOR with both inputs tied
    together
  • NAND and NOR are "duals",that is, its easy to
    implement one using the other

X Y X nand Y0 0 11 1 0
X Y X nor Y0 0 11 1 0
X nand Y ? not ( (not X) nor (not Y) ) X nor
Y ? not ( (not X) nand (not Y) )
6
Boolean Algbra
  • An algebraic structure consists of
  • a set of elements B B0, 1
  • binary operations , logical OR,
    logical AND
  • and a unary operation logical NOT
  • such that the following axioms hold
  • 1. the set B contains at least two elements a,
    b2. closure a b is in B a b is in B3.
    commutativity a b b a a b b a4.
    associativity a (b c) (a b) c a (b
    c) (a b) c5. identity a 0 a a 1
    a6. distributivity a (b c) (a b) (a
    c)
  • a (b c)
    (a b) (a c)7. complementarity a a
    1 a a 0

7
Axioms and theorems of Boolean algebra
  • identity 1. X 0 X 1D. X 1 X
  • null 2. X 1 1 2D. X 0 0
  • idempotency 3. X X X 3D. X X X
  • involution 4. (X) X
  • complementarity 5. X X 1 5D. X X
    0
  • commutativity 6. X Y Y X 6D. X Y
    Y X
  • associativity 7. (X Y) Z X (Y
    Z) 7D. (X Y) Z X (Y Z)
  • distributivity 8. X (Y Z) (X Y) (X
    Z) 8D. X (Y Z) (X Y) (X Z)

8
Axioms and theorems of Boolean algebra
  • uniting 9. X Y X Y X 9D. (X Y)
    (X Y) X
  • absorption 10. X X Y X 10D. X (X Y)
    X 11. (X Y) Y X Y 11D. (X Y) Y
    X Y
  • factoring 12. (X Y) (X Z) 12D. X Y
    X Z X Z X Y
    (X Z) (X Y)
  • concensus 13. (X Y) (Y Z) (X Z)
    13D. (X Y) (Y Z) (X Z)
    X Y X Z (X Y) (X
    Z)
  • de Morgans 14. (X Y ...) X Y ...
    14D. (X Y ...) X Y ...
  • generalized de Morgans 15. f(X1,X2,...,Xn,0,1,
    ,) f(X1,X2,...,Xn,1,0,,)

9
Axioms and theorems of Boolean algebra
  • Duality
  • a dual of a Boolean expression is derived by
    replacing by , by , 0 by 1, and 1 by 0,
    and leaving variables unchanged
  • any theorem that can be proven is thus also
    proven for its dual!
  • duality 16. X Y ... ? X Y ...
  • generalized duality 17. f (X1,X2,...,Xn,0,1,,)
    ? f(X1,X2,...,Xn,1,0,,)

10
Proving theorems (perfect induction)
  • Using perfect induction (complete truth table)
  • e.g., de Morgans

(X Y) X YNOR is equivalent to AND with
inputs complemented
1 0 0 0
1 0 0 0
(X Y) X YNAND is equivalent to OR with
inputs complemented
1 1 1 0
1 1 1 0
11
From Boolean expressions to logic gates
  • NOT X
  • AND X Y
  • OR X Y

X
Y
X
Z
Y
X
Z
Y
12
From Boolean expressions to logic gates
  • NAND
  • NOR
  • XOR X ??Y
  • XNOR X Y

X
Z
Y
X
Z
Y
X xor Y X Y X Y ("inequality",
"difference")
X
Z
Y
X
X xnor Y X Y X Y("equality", "coincidence")
Z
Y
13
From Boolean expressions to logic gates
  • More than one way to map expressions to gates
  • e.g., Z A B (C D) (A (B (C
    D)))

A
Z
A
B
B
Z
C
C
D
D
use of 3-input gate
14
Logic Blocks and Hierarchy
Example 2-input Binary Adder
2-bit Adder
A0
S0
A1
S1
B0
Cout
B1
15
Choosing different realizations of a function
0
1
0
1
0
1
A
B
C
two-level realization(we dont count NOT gates)
0
multi-level realization(gates with fewer inputs)
0
0
XOR gate (easier to draw but costlier to build)
16
Canonical forms
  • Truth table is the unique signature of a Boolean
    function
  • The same truth table can have many gate
    realizations
  • Canonical forms
  • standard forms for a Boolean expression
  • provides a unique algebraic signature
  • Sum of product
  • Product of sum

17
Sum-of-products canonical forms
  • Also known as disjunctive normal form
  • Also known as minterm expansion

0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
F A' B C A B' C' A B' C A B C'
A B C
F' A' B' C' A' B' C A' B C'
18
Sum-of-products canonical form
  • Product term (or minterm)
  • ANDed product of literals input combination for
    which output is true
  • each variable appears exactly once, true or
    inverted (but not both)

F in canonical form F(A, B, C)
?m(1,3,5,6,7) m1 m3 m5 m6 m7
ABC ABC ABC ABC ABC
canonical form ? minimal form F(A, B, C)
ABC ABC ABC ABC ABC (AB AB
AB AB)C ABC ((A A)(B B))C ABC
C ABC ABC C AB C
short-hand notation forminterms of 3 variables
19
Product-of-sums canonical form
  • Also known as conjunctive normal form
  • Also known as maxterm expansion

F 000 010 100F

F (A B C) (A B C) (A B C) (A
B C) (A B C)
20
SOP POS Minterm Maxterm
  • The translation method used in previous example
    is Sum of Product
  • SOP is the SUM of AND products, and equals F
    (the output)
  • e.g., F ABC ABC ABC ABC ABC
  • Each product in a SOP is called a Minterm (or,
    standard product)
  • Another translation method is Product of Sum
  • Pick up all these input combinations which
    produce logic low output (0 or false state)
  • e.g., F ABC ABC ABC in the
    previous example
  • F ABC ABC ABC
  • F (A B C)(A B C)(A B C)
  • 1. applying DeMorgan Theorem, (X Y) XY
    F ABC ABC ABC
    (ABC)(ABC)(ABC)
  • 2. applying DeMorgan Theorem, (XY) (X Y)
    F (ABC)(ABC)(ABC) (A B C)(A B
    C)(A B C)
  • So, a POS function is a AND product of OR
    sums.
  • Each sum in a POS is called a Maxterm (or,
    standard sum)
  • Further simplying the above POS function gives F
    BC A .... try proving it!

21
SOP and POS
  • Minterms and Maxterms can be shown in a truth
    table, or, by using Boolean Expression
  • e.g. F ABCABCABCABCABC
  • e.g. F (ABC)(ABC)(ABC)
  • Alternately, the same SOP can be expressed as
    F(A, B, C) ?( 3, 4, 5, 6, 7). The decimal
    number inside the bracket refers to the
    corresponding Minterms of F
  • e.g. 3 refers to ABC (011)
  • Likewise, the Maxterms can be expressed as F(A,
    B, C) ?(0, 1, 2)

22
K-Map and Boolean Expression - 1
  • What is a K-Map or Karnaugh Map a map which
    shows the relation between the input and output
    of a logic expression. Its function is like a
    truth table.
  • Truth table uses input and output columns.
  • K-Map uses X-Y or vertical-horizontal
    coordinates to represent a specific combination
    of input and puts the corresponding output in
    that coordinate, or, cell.
  • For a K-map to show logic AND, the cell AB shall
    be marked 1, all other cells be marked 0.
  • Likewise, a K-map with 1 in all cells except
    the cell AB represents the logic OR.
  • A K-Map has 4 cells for 2 input variables, 8
    cells for 3 and 16 cells for four .....

23
K-Map and Boolean Expression - 2
  • The coordinates of a K-Map is in gray code
    format, i.e. two adjacent cells shall have only
    one variable changing. This is for easy grouping
    - to be taught next page.
  • Picking up all these cells which has a 1, we
    get the following boolean expression
  • F ABCD ABCD
  • ABCD ABCD ABCD
  • ABCD ABCD ABCD ABCD
  • ABCD ABCD ABCD
  • Picking up all cells which has a 0, we have
  • F ABCD ABCD ABCD ABCD

24
K-Map Grouping Minimisation
  • By grouping adjacent cells of same logic state
    together we can simplify the logic expression.
  • Grouping TWO cells
  • e.g., ABCD and ABCD in 2nd row
  • F .... (ABCD ABCD) ...
  • F .... (ACD) ....
  • Grouping FOUR cells
  • e.g., ABCD, ABCD, ABCD and ABCD in 3rd row
  • F .... (ABCD ABCD ABCD ABCD) ....
  • F .... (ACD ACD) ....
  • F .... (CD) ....

F ?
25
K-Map Grouping Minimisation
  • Find out all the possible groupings and derive
    the equivalent logic expression

26
K-Map Grouping Minimisation
  • Find out all the possible groupings and derive
    the equivalent logic expression
  • Group 1 8 cells of column 00 and 01 A

27
K-Map Grouping Minimisation
  • Find out all the possible groupings and derive
    the equivalent logic expression
  • Group 1 8 cells of column 00 and 10 A
  • Group 2 4 cells of column 00 and 10 row 00
    and 01 BC

28
K-Map Grouping Minimisation
  • Find out all the possible groupings and derive
    the equivalent logic expression
  • Group 1 8 cells of column 00 and 10 A
  • Group 2 4 cells of column 00 and 10 row 00
    and 01 BC
  • Group 3 4 cells at the four corners BD

29
K-Map Grouping Minimisation
  • Find out all the possible groupings and derive
    the equivalent logic expression
  • Group 1 8 cells of column 00 and 10 A
  • Group 2 4 cells of column 00 and 10 row 00
    and 01 BC
  • Group 3 4 cells at the four corners BD
  • so, F A BC BD

30
Group size vs No. of variables
  • For a 4 by 4 K-map
  • a 1-cell group concerns 4 variables
  • a 2-cell group concerns 3 variables
  • a 4-cell group concerns 2 variables
  • a 8-cell group concerns 1 variable only
  • Can we group 3, 5, 6 adjacent cells?
  • e.g. (ABCD ABCD ABCD)
  • ABCD ABC AB(CD C)
  • ABC ABD
  • The result is same as having TWO groups!
  • So, always use the group size of 2, 4, 8, ...
  • If all cells in a K-map are filled by 1,
  • what is the logic expression then? F ?

?
1 group of 3 cells or 2 groups of 2 cells each ?
31
K-map - Rules of Grouping
  • All 1s (or 0s) shall be picked up, dont leave
    any cell unattended.
  • As small number of group as possible
  • Each group - as large as possible
  • Groups can overlap
  • Dont create sub-group a small group totally
    within a larger group
  • Depend on the distribution of 1 0, it may
    be better to pick up 0s to find F first.
  • e.g. F BCD ABD
  • F (BCD)(ABD) (B C D)(A B D)

Which is easiler, grouping 1 or 0 ?
32
K-map vs Truth Table
  • After filling in a truth table base on a SOP
    expression F(A,B,C,D) ?(0, 1, 2, 4, 5, 6, 8, 9,
    12, 13, 14), can you easily derive the boolean
    expression F then?
  • Now, try fill in the SOP expression in a K-map.
  • remember the numbers in the bracket refers to the
    minterms of F, all of which is logic 1
  • convert these decimal numbers to binary form in
    order to find out the cell locations.
  • So, by using K-map derive the boolean expression
    for the above SOP expression.
  • F ?
  • As for POS expression, put 0 into the
    appropriate cells.

Decimal number shown above are based on ABCD A
being MSB and D being LSB
33
K-map vs Truth Table
  • After filling in a truth table base on a SOP
    expression F(A,B,C,D) ?(0, 1, 2, 4, 5, 6, 8, 9,
    12, 13, 14), can you easily derive the boolean
    expression F then?
  • Now, try fill in the SOP expression in a K-map.
  • remember the numbers in the bracket refers to the
    minterms of F, all of which is logic 1
  • convert these decimal numbers to binary form in
    order to find out the cell locations.
  • Hopefully, you can easily derive the boolean
    expression as F C AD BD

1 1 1 1
1 1 1 1
0 0 0 0
1 1 1 0
Decimal number shown above are based on ABCD A
being MSB and D being LSB
34
Implementation of SOP POS - 1
  • using SOP method, F BC BD ACD
  • using POS method, F AB CD BD
  • F (A B)(C D)(B D)
  • we can then use a combination of OR, AND and NOT
    gates to implement the logic circuit

35
Implementation of SOP POS - 2
  • We can also implement SOP and POS using either
    NAND gates only or NOR gates only ..... remember
    how NAND gates can perform OR gate function
  • Is it sensible just to replace all the OR and AND
    gates of the circuit shown in previous page, with
    NAND gates?
  • No? Why?
  • We should use DeMorgans theorem to do the
    following conversion
  • complement F twice, so, F BC BD ACD
    (BC BD ACD)
  • but (BC BD ACD) (BC)(BD)(AC
    D)
  • so, we get rid of the OR function
  • likewise, F (A B)(C D)(B D)
  • F (A B) (C D) (B D)
  • so, we get rid of the AND function

36
Dont Care Term
  • As for the previous example of door alarm system
  • If we do not make use of the dont care term, the
    logic expression is derived as F ABC ABC
  • If we use the dont care term, then, we have F
    BC AC, or,
  • Again, if take the maxterm first
  • F C AB
  • F (C AB) BC AC
  • Using SOP and POS shall get the same result of F.

not grouping dont care term
grouping dont care term
37
Dont Care Term
  • Compare the logic expression derived taking the
    dont care terms as 1 with that of taking the
    dont care terms as 0. Will they be equals?
  • F CD AD D(A C)
  • F D BC F D(B C)
  • The two logic expressions are different simply
    because we take ABCD 1 for the first case and
    0 for the other.

38
Four Variable Map
Y
YZ
0 0 0 1 1 1 10
WX
m0 m1 m3 m2 m4 m5 m7 m6
00
01
m12 m13 m15 m14 m8 m9
m11 m10
X
11
w x yz
W
10
Z
39
Four Variable Map
N 4 variables 2N 24 16 square (minterms)
Row and column are numbered using a
reflected-code Sequence. The minterm number
can be obtained by concatenation Of the row and
column number . Example Row 4 10, Column 2
01 giving 1001 9 decimal for W X Y Z.
40

Y
YZ
0 0 0 1 1 1 10
wxyz
wxy z
00
01
X
11
W
10
Z
Notice that top and bottom edges and right and
left edges are adjacent.
41
1 square a term with 4 literals 2 square a
term with 3 literal 4 square a term with 2
literals 8 square a term with 1 literal 16
square a function equal to 1
Y
YZ
0 0 0 1 1 1 10
WX
00
01
X
11
W
10
Z
42
Simplify f (W, X, Y, Z) W X Z W X Z W Y
Z f W Z Y Z f Z ( W Y)
Y
YZ
0 0 0 1 1 1 10
WX
00
01
X
11
W
10
Z
43
Simplify f (W, X, Y, Z) ? ( 0, 1, 4, 5, 6, 8,
9, 12, 13, 14) f Y WZ XZ
Y
YZ
0 0 0 1 1 1 10
WX
00
01
X
11
W
10
Z
8 square 4 square
4 square
44
Simplify f W X Y XY Z W X Y Z W
X Y f X Z X Y
W Y Z
Y
YZ
0 0 0 1 1 1 10
WX
00
01
X
11
W
10
Z
45
Four Variable Map
COMPLEMENT PRODUCT OF SUMS On the K Map a 1 was
placed in the squares which represented minterms
for a function. The squares not used represent
the complement of the function. Mark these
squares with 0, combine them and read the
complement as a sum of products function, f.
Using De Morgans Law on f will give f, the
original Function. It will be in a product of
sums form. Example Determine the Product of
sums form for f ( W, X, Y, Z) ? (0, 1, 2, 5, 8,
9, 10) f W X YZ X Z from the map f
(W X) ( Y Z) ( X Z) by De Morgans
46
Also, can determine the product of sums form
directly from The map by recognizing that the 0s
on the map represent maxterms. Remember that a 1
on the edge of the map Represents a complemented
literal for maxterms. Thus, for f ( W, X, Y, Z)
? (0, 1, 2, 5, 8, 9, 10).
f ( Y Z) (W X) ( X Z) (see map)
47
Y
YZ
0 0 0 1 1 1 10
WX
1 1 0 1
00
0 1 0 0
01
11
0 0 0 0
W
10
1 1 0 1
Z
f ( Y Z ) ( W X ) ( X Z)
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61
Parallel Computers
  • Definition A parallel computer is a collection
    of processiong elements that cooperate and
    communicate to solve large problems fast.
  • Almasi and Gottlieb, Highly Parallel Computing
    ,1989
  • Questions about parallel computers
  • How large a collection?
  • How powerful are processing elements?
  • How do they cooperate and communicate?
  • How are data transmitted?
  • What type of interconnection?
  • What are HW and SW primitives for programmer?

62
Parallel Processors Religion
  • The dream of computer architects since 1950s
    replicate processors to add performance vs.
    design a faster processor
  • Led to innovative organization tied to particular
    programming models since uniprocessors cant
    keep going
  • e.g., uniprocessors must stop getting faster due
    to limit of speed of light 1972, , 1989
  • Borders religious fervor you must believe!
  • Fervor damped some when 1990s companies went out
    of business Thinking Machines, Kendall Square,
    ...

63
What level Parallelism?
  • Bit level parallelism 1970 to 1985
  • 4 bits, 8 bit, 16 bit, 32 bit microprocessors
  • Instruction level parallelism (ILP) 1985
    through today
  • Pipelining
  • Superscalar
  • VLIW
  • Out-of-Order execution
  • Limits to benefits of ILP?

64
Why Multiprocessors?
  • Microprocessors as the fastest CPUs
  • Collecting several much easier than redesigning 1
  • Complexity of current microprocessors
  • Do we have enough ideas to sustain 1.5X/yr?
  • Can we deliver such complexity on schedule?
  • Slow (but steady) improvement in parallel
    software (scientific apps, databases, OS)

65
Popular Flynn Categories
  • SISD (Single Instruction Single Data)
  • Uniprocessors
  • MISD (Multiple Instruction Single Data)
  • ??? multiple processors on a single data stream
  • SIMD (Single Instruction Multiple Data)
  • Examples Illiac-IV, CM-2
  • Simple programming model
  • Low overhead
  • Flexibility
  • All custom integrated circuits
  • (Phrase reused by Intel marketing for media
    instructions vector)
  • MIMD (Multiple Instruction Multiple Data)
  • Examples Sun Enterprise 5000, Cray T3D, SGI
    Origin
  • Flexible
  • Use off-the-shelf micros
  • MIMD current winner Concentrate on major design
    emphasis lt 128 processor MIMD machines

66
SISD
One piece of data is sent to one processor.
Ex To multiply one hundred numbers by the number
three, each number would be sent and calculated
until all one hundred results were calculated.
67
MISD
One piece of data is broken up and sent to many
processor.
CPU
Data
CPU
Search
CPU
CPU
Ex A database is broken up into sections of
records and sent to several different processor,
each of which searches the section for a specific
key.
68
SIMD
Multiple processors execute the same instruction
of separate data.
Ex A SIMD machine with 100 processors could
multiply 100 numbers, each by the number three,
at the same time.
69
MIMD
Multiple processors execute different instruction
of separate data.
CPU
Data
Multiply
CPU
Data
Search
CPU
Data
Add
CPU
Data
Subtract
This is the most complex form of parallel
processing. It is used on complex simulations
like modeling the growth of cities.
70
MIMD computers usually have a different program
running on every processor. This makes for a
very complex programming environment.
Whats doing what when?
What processor? Doing which task? At what time?
71
Memory latency
The time between issuing a memory fetch and
receiving the response.
Simply put, if execution proceeds before the
memory request responds, unexpected results will
occur. What values are being used? Not the
ones requested!
72
A similar problem can occur with instruction
executions themselves.
Synchronization The need to enforce the ordering
of instruction executions according to their data
dependencies.
Instruction b must occur before instruction a.
73
Despite potential problems, MIMD can prove larger
than life.
MIMD Successes
IBM Deep Blue Computer beats professional chess
player.
Some may not consider this to be a fair example,
because Deep Blue was built to beat Kasparov
alone. It knew his play style so it could
counter is projected moves. Still, Deep Blues
win marked a major victory for computing.
74
IBMs latest, a supercomputer that models nuclear
explosions.
IBM Poughkeepsie built the worlds fastest
supercomputer for the U. S. Department of Energy.
Its job was to model nuclear explosions.
75
MIMD its the most complex, fastest, flexible
parallel paradigm. Its beat a world class chess
player at his own game. It models things that
few people understand. It is parallel processing
at its finest.
76
Major MIMD Styles
  • Centralized shared memory ("Uniform Memory
    Access" time or "Shared Memory Processor")
  • Decentralized memory (memory module with CPU)
  • get more memory bandwidth, lower memory latency
  • Drawback Longer communication latency
  • Drawback Software model more complex
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