Cache Memory Midterm 2 Revision 2

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Cache MemoryMidterm 2 Revision 2
Lecture 15

• Prof. Sin-Min Lee
• Department of Computer Science

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The Processor Picture
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The Five Classic Components of a Computer
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von NeumannArchitecturePrinceton
Memory
Address Pointer
Arithmetic Logic Unit (ALU)
Data/Instructions
Pc Pc 1
Program Counter
Featuring Deterministic Execution
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Cache Memory

• Physical memory is slow (more than 30 times
  slower than processor)
• Cache memory uses SRAM chips.
• Much faster
• Much expensive
• Situated closest to the processor
• Can be arranged hierarchically
• L1 cache is incorporated into processor
• L2 cache is outside

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Cache Memory

• This photo shows level 2 cache memory on the
  Processor board, beside the CPU

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Cache Memory- Three LevelsArchitecture
Memory Multi- Gigabytes Large and Slow 160 X
Cache Control Logic
2 Gigahertz Clock
8X
2X
16X L3 Cache Memory
L2 Cache Memory
L1 Cache Memory
32 Kilobytes
128 Kilobytes
16 Megabytes
Featuring Really Non-Deterministic Execution
Address Pointer
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Cache (1)

• Is the first level of memory hierarchy
  encountered once the address leaves the CPU
• Since the principle of locality applies, and
  taking advantage of locality to improve
  performance is so popular, the term cache is now
  applied whenever buffering is employed to reuse
  commonly occurring items
• We will study caches by trying to answer the four
  questions for the first level of the memory
  hierarchy

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Subtract by Summation

• Subtraction with complement is done with binary
  numbers in a similar way.
• Using two binary numbers X1010100 and Y1000011
• We perform X-Y and Y-X

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X-Y

• X 1010100
• 2s com. of Y 0111101
• Sum 10010001
• Answer 0010001

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Y-X

• Y 1000011
• 2s com. of X 0101100
• Sum 1101111
• Theres no end carry answer is negative ---
  0010001 (2s complement of 1101111)

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How To Represent Signed Numbers

• Plus and minus signs used for decimal numbers
  25 (or 25), -16, etc.
• For computers, it is desirable to represent
  everything as bits.
• Three types of signed binary number
  representations
• signed magnitude,
• 1s complement, and
• 2s complement

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1. signed magnitude

• In each case left-most bit indicates sign
  positive (0) or negative (1).

Consider 1. signed magnitude
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2. Ones Complement Representation

• The ones complement of a binary number involves
  inverting all bits.
• To find negative of 1s complement number take
  the 1s complement of whole number including the
  sign bit.

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3. Twos Complement Representation

• The twos complement of a binary number involves
  inverting all bits and adding 1.
• To find the negative of a signed number take the
  2s the 2s complement of the positive number
  including the sign bit.

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Sign addition in 2s complement
The rule for addition is add the two numbers,
including their sign bits, and discard any carry
out of the sign (leftmost) bit position.
Numerical examples for addition are shown
below. Example 6 00000110 -
6 11111010 13 00001101 13 00001101 19 0001
0011 7 00000111 6 00000110 -6 11111010 -1
3 11110011 -13 11110011 -7 11111001 -19 111
01101 In each of the four cases, the operation
performed is always addition, including the sign
bits. Only one rule for addition, no separate
treatment of subtraction. Negative numbers are
always represented in 2s complement.
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Arithmetic Subtraction

• A subtraction operation can be changed to an
  addition operation if the sign of the subtrahend
  is changed.
• (A) - (B) (A) (-B)
• (A) - (-B) (A) (B)

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Arithmetic Subtraction

• Consider the subtraction of (-6) - (-13) 7. In
  binary with eight bits this is written as
  11111010 - 11110011. The subtraction is changed
  to addition by taking the 2s complement of the
  subtrahend (-13) to give (13). In binary this is
  11111010 00001101 100000111.
• Removing the end carry, we obtain the correct
  answer 00000111 ( 7).

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4 to 1 MUX
DataFlow
D3D0
Dout
4
Control
4
2 - 4 Decoder
Sel(30)
2
S1S0
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4-to-1 MUX (Gate level)
Control Section
Three of these signal inputs will always be 0.
The other will depend on the data value selected
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Multiplexer (cont.)

• Until now, we have examined single-bit data
  selected by a MUX. What if we want to select
  m-bit data/words?? Combine MUX blocks in
  parallel with common select and enable signals
• Example Construct a logic circuit that selects
  between 2 sets of 4-bit inputs (see next slide
  for solution).

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Example Quad 2-to-1 MUX

• Uses four 4-to-1 MUXs with common select (S) and
  enable (E).
• Select line chooses between Ais and Bis. The
  selected four-wire digital signal is sent to the
  Yis
• Enable line turns MUX on and off (E1 is on).

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Implementing Boolean functions with Multiplexers

• Any Boolean function of n variables can be
  implemented using a 2n-1-to-1 multiplexer. A MUX
  is basically a decoder with outputs ORed
  together, hence this isnt surprising.
• The SELECT signals generate the minterms of the
  function.
• The data inputs identify which minterms are to be
  combined with an OR.

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Example

• F(X,Y,Z) XYZ XYZ XYZ XYZ
  Sm(1,2,6,7)
• There are n3 inputs, thus we need a 22-to-1 MUX
• The first n-1 (2) inputs serve as the selection
  lines

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Efficient Method for implementing Boolean
functions

• For an n-variable function (e.g., f(A,B,C,D))
• Need a 2n-1 line MUX with n-1 select lines.
• Enumerate function as a truth table with
  consistent ordering of variables (e.g., A,B,C,D)
• Attach the most significant n-1 variables to the
  n-1 select lines (e.g., A,B,C)
• Examine pairs of adjacent rows (only the least
  significant variable differs, e.g., D0 and D1).
• Determine whether the function output for the
  (A,B,C,0) and (A,B,C,1) combination is (0,0),
  (0,1), (1,0), or (1,1).
• Attach 0, D, D, or 1 to the data input
  corresponding to (A,B,C) respectively.

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Another Example

• Consider F(A,B,C) ?m(1,3,5,6). We can implement
  this function using a 4-to-1 MUX as follows.
• The index is ABC. Apply A and B to the S1 and S0
  selection inputs of the MUX (A is most sig, S1 is
  most sig.)
• Enumerate function in a truth table.

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MUX Example (cont.)
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
When AB0, FC
When A0, B1, FC
When A1, B0, FC
When AB1, FC
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MUX implementation of F(A,B,C) ?m(1,3,5,6)
A
B
C
C
F
C
C
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These pictures have errors.
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2 Input Multiplexor
Inputs I0 and I1 Selector S Output O If S is
a 0 OI0 If S is a 1 OI1
Mux
I0
O
I1
S
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2-Mux Logic Design
I1
I0
S
I0 !S
O
I1 S
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4 Input Multiplexor
Inputs I0 I1 I2 I3 Selectors S0 S1 Output O
Mux
I0
I1
O
I2
S0 S1 O
0 0 I0
0 1 I1
1 0 I2
1 1 I3
I3
S0
S1
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One Possible 4-Mux
2-Decoder
S0
I0
I1
S1
O
I2
I3
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Adder

• We want to build a box that can add two 32 bit
  numbers.
• Assume 2s complement representation
• We can start by building a 1 bit adder.

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Addition

• We need to build a 1 bit adder
• compute binary addition of 2 bits.
• We already know that the result is 2 bits.

A B O0 O1
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
This is addition!
A B O0 O1
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One Implementation
A B
A
O0
B
!A
(!A B) (A !B)
B
O1
A
!B
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Binary addition and our adder
1
1
Carry
01001 01101
10110

• What we really want is something that can be used
  to implement the binary addition algorithm.
• O0 is the carry
• O1 is the sum

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What about the second column?
1
1
Carry
01001 01101
10110

• We are adding 3 bits
• new bit is the carry from the first column.
• The output is still 2 bits, a sum and a carry

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Truth Table for Addition
A B Carry In Carry Out Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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Synchronous Sequential Circuit with T Flip-Flop --
Figure 8.12
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Timing Diagram
Figure 8.13
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State Table and State Diagram
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K-Maps for Example
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Example 2.Synchronous Sequential Circuit with JK
Flip-flops
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Timing Diagram and State Table for Example 2
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K-Maps for Example 2
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Generating the State Table From K-maps --
Example 2
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Example 3.Synchronous Sequential Circuit Synthesis
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Introductory Synthesis Example -- Example 3
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Flip-flop Input Tables -- Example 3
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Generating the JK Flip-flop Excitation Maps
--Example 3
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Clocked JK Flip-Flop Implementation --Example 3
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Application Equation Method for Deriving
Excitation Equations -- Example 3
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Registers

• Two independent flip-flops with clear and preset

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Using T Flip Flop and JK Flip Flop

• log24 2, so 2 flip flops are needed to
  implement this FSA

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Step 1 - Translate diagram into StateTable

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Step 2 - Create maps for T and JK

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Step 3 - Determine T, J, and K equations

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Step 4 - Draw resulting diagram

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