Logic Simulator for Hierarchical Bench

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Logic Simulator for Hierarchical Bench

• Hillary Grimes III Term Project
• ELEC 7250 Spring 2006

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Problem Statement

• Develop a Logic Simulator for Zero-Delay Boolean
  gates to perform circuit verification.
• Inputs --Hierarchical Bench Circuit
  Description --Input Vectors and Expected Outputs
• Outputs when Simulation Fails --Inputs and
  Outputs with failed responses --Diagnosis
  Information

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Circuit Representation in C

• Each hierarchical block is stored as an element
  in a block array containing --block
  name --input signal list --array of
  gates --output signal list

• Signals Contain --signal name --level --value

• Gates Contain --gate name --gate
  type --level --input signal list --output
  signal list --fan in array

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Building the Block Array

• Each block is flattened as it is read in
• After POs and PIs are assigned, the gate array is
  built. Each line from the netlist is either a
  boolean gate, or a previously defined block. -If
  boolean gate add to gate array --gate name
  g0, g1, g2, etc --assign input and output
  signals -If not boolean insert block from
  previous elements in block array

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Insert Gates for an XOR Block
XOR Description Inputs A, B Output Y
X1NAND(A,B) X2NAND(X1,A)
X3NAND(X1,B) YNAND(X2,X3)
XOR Blocks gate array contains g0 NAND
g1 NAND Inputs A, B Inputs X1,
A Output X1 Output X2 g2
NAND g3 NAND Inputs X1, B
Inputs X2, X3 Output X3 Output
Y
OUT XOR ( IN_1, IN_2) Inserts Gates
XOR0.g0 NAND XOR0.g1 NAND
Inputs IN_1, IN_2 Inputs
XOR0.X1, IN_1 Output XOR0.X1
Output XOR0.X2 XOR0.g2 NAND XOR0.g3
NAND Inputs XOR0.X1, IN_2
Inputs XOR0.X2, XOR0.X3 Output XOR0.X3
Output OUT
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Level Block

• Gates are inserted into gate array such that each
  gates inputs are either PIs, or an output of a
  previous gate.
• To levelize a block, we visit each gate in
  increasing order --level of gate max level of
  input signals --level of gates output 1gate
  level
• --increasing order ensures that each input
  has an assigned level

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Simulation

• To simulate a block given an input
  vector --assign signal values to primary
  inputs --visit each gate in gate array
  (increasing order) -evaluate and assign gates
  output signal
• Diagnose if output differs from the expected
  response --diagnoses starts at each failing PO
  and back tracks through the circuit --informat
  ion (including signal values) for each gate
  along a path to the failing PO is printed

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Results
Circuit Number of Gates Number of Inputs Number of Outputs Execution Time (msec)
c17 6 5 2 0
c432 120 36 7 63
c499 162 41 32 141
c880 320 60 26 110
c1355 506 41 32 172
c1908 603 33 25 250
c2670 872 233 140 438
c3540 1179 50 22 485
c5315 1726 178 123 797
c6288 2384 32 32 781
c7552 2636 207 108 1125
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Results
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Conclusion

• Execution times seem to grow with both the number
  of gates, and the number of inputs/outputs
• Diagnosis still needs work --if multiple paths
  to the failing PO include the same gate, that
  gates information is printed multiple
  times. --diagnostic resolution could be much
  better with a better algorithm