ELEC7250 VLSI Testing: Final Project

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ELEC7250 VLSI TestingFinal Project

• Andrew White

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Overview

• Problem Description
• Plan
• Results
• Demonstration

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Plan

• Compiler
• Hierarchical bench formats are flattened
• Logic Simulator
• Used simulation table and test vectors
• Two states (1,0)

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Plan

• Algorithm
• Input vector is propogated through to the output
• Traverse through the gates in levels

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Results
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Results
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Plan

• Due to long logic simulations
• Parallelize the problem
• Parallel Approach
• Same algorithm as the sequential approach
• Main node broadcasts the simulation table to all
  other nodes
• Main node reads in test vector file and evenly
  distributes vectors to all other nodes
• Each node computes vector values and reports the
  results to the main node

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Results
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Fault Diagnosis

• Find faulty vector
• Find faulty outputs
• Algorithm complexity

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Demonstration
C17 Circuit
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Conclusion

• Questions/Comments?