Logic simulator and fault diagnosis

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Logic simulator and fault diagnosis

• Fan Wang
• Dept. of Electrical Computer Engineering
• Auburn University
• ELEC7250 Term Project Spring 06

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Motivations

• Write a compiler for the hierarchical bench
  format.
• Write a logic simulator for combinational circuit
• Attempt to diagnose the design error

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Compiler
Simulation table Example (generated by
matlab) INPUT 0 INPUT 1 INPUT 2 OUTPUT
15 OUTPUT 16 Gatetype XOR Gatename
XOR1 Fanin_List 2 1 Fanout_List
FA_1_1 // Gatetype
AND Gatename AND1 Fanin_List 1 2 Fanout_List
FA_1_2 // Gatetype
AND Gatename AND2 Fanin_List 0
FA_1_1 Fanout_List FA_1_3 /
/ Gatetype XOR Gatename XOR2 Fanin_List
FA_1_1 0 Fanout_List 3 /
/

• For hierarchical bench format, the compiler can
  flatten it
• Compiler can use flattened netlist to generate
  the simulation table
• For convenience, this part is implemented by
  Matlab.

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Logic Simulation

• Read vector to the PI
• Initialize all the PO, Internal nodes as unknown
  states (-1).
• Propagate the value from PI to PO.
• For each unknown internal node, search all
  file until it gets value. If all the PO get
  value, step 3 end.
• Repeat 1 to get the next vector.
• Implemented by C program

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Logic Simulation (Cont.)
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Some Comments on logic simulator

• The search based algorithm
• Time complexity is O( ), N the number of
  gates. The worst case is, all gates are list in
  reverse order. The time complexity is
• The depth of circuit x
• 2. The levelization of the circuit, the time
  complexity will the same as the logic simulation
  based search based algorithm
• Better algorithm can be used link list based
  algorithm

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Diagnosis (Sensitized Path Segmentation PO
trace back)

• Check PO, see whether the PO get values as
  expected
• If error happens
• 1. trace back from the error PO to PI to
  check the paths (PATH 1).
• 2. check which path is sensitized by the
  vector from PI to PO (PATH 2).
• The error is on the path PATH 1 PATH2
• Not for multiple fault diagnosis

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Sensitized path segmentation
Design error OR --gt AND !!
1
and1
5
or1
2
p3
p2
8
10
3
9
p1
xor1
and2
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(PI) 1 2 3 4 (PO Good Value) (PO Bad Value)
V1 0 0 0 1 0 0
V2 0 0 1 1 0 1
V3 1 1 1 1 0 0
V4 1 0 1 1 0 1
Based on 4 vectors error is on p3 p2 p1
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• Thanks!