CPU Design Project Synthesis Report

1
CPU Design ProjectSynthesis Report

• ELEC 7770-001 - Dr. Agrawal
• Lee W. Lerner
• April 24, 2007

2
Outline

• Synthesis Goals
• Synthesis Design Flow
• Mentor Graphics IC Flow Design Tools
• Various other software tools used for design
  debugging and verification
• Synthesis Results
• Area and Delay reports
• Netlist verification
• Conclusions
• Suggestions for improvement

3
Synthesis Goals

• Take a verified design modeled in hardware
  description language (VHDL in our design project)
• Generate a gate- level netlist for the circuit
  that optimizes either
• 1. Area
• 2. Delay
• 3. Both (to a lesser extent)
• Verify functionality of netlists generated
• Decide on synthesized netlist to proceed with in
  project design flow

4
Synthesis Design Flow

• Mentor Graphics IC Design Flow tools used
• Leonardo Spectrum 8
• Synthesize gate-level netlists optimized for area
  and delay from provided VHDL CPU design
• Flextest
• Verify that synthesized gate-level netlists
  compile

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Synthesis Design Flow

• Leonardo Spectrum 8

V. P. Nelson, Tutorial Documents for Mentor
Graphics Tools, http//www.eng.auburn.edu/de
partment/ee/mgc/mentor.html
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Synthesis Design Flow

• Netlists generated and corresponding reports
• 1. Area Optimization (CPU_areaOpt.edf)
• Area report areaOpt_areaReport
• Delay report areaOpt_delayReport
• 1. Delay Optimization (CPU_delayOpt.edf)
• Area report delayOpt_areaReport
• Delay report delayOpt_delayReport

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Synthesis Results

• areaOpt_areaReport

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Synthesis Results

• areaOpt_delayReport

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Synthesis Results

• delayOpt_areaReport

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Synthesis Results

• delayOpt_delayReport

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Synthesis Results

• Netlist comparison

Area Optimization Number of ports 111
Area Optimization Number of nets 8249
Area Optimization Number of instances 7601
Area Optimization Number of references to this view 0
Area Optimization Number of gates 16264
Area Optimization Number of accumulated instances 7601
Area Optimization data arrival time 18.06 ns
Delay Optimization Number of ports 111
Delay Optimization Number of nets 8343
Delay Optimization Number of instances 7696
Delay Optimization Number of references to this view 0
Delay Optimization Number of gates 16280
Delay Optimization Number of accumulated instances 7696
Delay Optimization data arrival time 18.22 ns
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Synthesis Results

• Synthesis Verication FlexTest

• Netlists compile correctly

• Need for DFT (scan design)

13
Conclusions

• Used Leonardo Spectrum 8 to generate gate-level
  netlists optimized for area and delay
  independently
• Netlists compile correctly
• Due to area and delay similarity between
  generated netlists it was decided that we could
  proceed with either netlist in the design project

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Conclusions

• Suggestions for improvement
• Improved communication between team members (i.e.
  weekly status reports/presentations)
• Every team member has input at each stage in the
  design
• Identify coding and design errors earlier
• Identify need for and implement DFT before
  synthesis
• Improved CPU design in a shorter time