Course web page:

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ECE 545 Introduction to VHDL
Course web page
ECE web page ? Courses ? Course web pages ? ECE
545
http//ece.gmu.edu/courses/ECE545/index.htm
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Kris Gaj

• Research and teaching interests
• reconfigurable computing
• computer arithmetic
• cryptography
• network security
• Contact
• Science Technology II, room 223
• kgaj01_at_yahoo.com, kgaj_at_gmu.edu
• [phone]

Office hours Monday, Wednesday 730-830 PM
and by appointment
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ECE 545
Part of
MS in Computer Engineering
Required course in two concentration areas
Digital Systems Design Microprocessor and
Embedded Systems
Elective course in the remaining concentration
areas
MS in Electrical Engineering
Elective
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Fall 2005 Enrollment as of August 31, 2005
MS in IS 1
PhD in IT 1
PhD in ECE 1
MS in CpE 13
MS in EE 12
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Courses
Design level
Computer Arithmetic
Introduction to VHDL
VLSI Test Concepts
VLSI Design Automation
algorithmic
ECE 645
ECE 681
ECE 545
register-transfer
ECE 682
gate
ECE 586
Digital Integrated Circuits
transistor
ECE 699
layout
MixedSignals VLSI
MOS Device Electronics
Semiconductor Device Fundamentals
ECE684
ECE 584
devices
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Core courses

• There are TWO core courses common for all
  concentration
• areas
• CS 571 Operating Systems H. Aydin, S. Setia,
  C. Snow, project, C/C or Java
• Pros
• Prerequisite for many other courses and projects
• HLL (High Level Language) refresher
• Offered regularly in Fall and Spring
• ECE 548 Sequential Machine Theory K. Hintz,
  R. Schneider
• Pros
• Common theoretical and mathematical foundation
  used in all
• concentrations
• Offered regularly in Spring
• Not a strong prerequisite for any other course
  can be taken any time
• during the curriculum.

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• DIGITAL SYSTEMS DESIGN
• Concentration advisor Ken Hintz
• 1. ECE 545 Introduction to VHDL K. Gaj, K.
  Hintz, projects, VHDL, Aldec/Synplicity/Xilinx
  and ModelSim/Synopsys
• 2. ECE 645 Computer Arithmetic HW and SW
  Implementation K. Gaj, projects, VHDL,
  Aldec/Synplicity/Xilinx and
  ModelSim/Synopsys
• 3. ECE 586 Digital Integrated Circuits D.
  Ioannou
• 4. ECE 681 VLSI Design Automation K. Kazi,
  projectz, VHDL, ModelSim/Synopsys

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• MICROPROCESSOR AND EMBEDDED SYSTEMS
• Concentration advisor Peter Pachowicz
• ECE 511 Microprocessors R. Barnes, P.
  Pachowicz,
• ECE 545 Introduction to VHDL K. Gaj, K. Hintz,
  project, VHDL, Aldec/Synplicity/Xilinx and
  ModelSim/Synopsys
• ECE 611 Advanced Microprocessors R. Barnes, D.
  Tabak
• ECE 612 Real-Time Embedded Systems K. Hintz

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• MICROPROCESSOR AND EMBEDDED SYSTEMS
• Concentration advisor Peter Pachowicz
• ECE 511 Microprocessors P. Pachowicz
• ECE 545 Introduction to VHDL K. Hintz, K. Gaj,
  project, VHDL, Aldec/ModelSim,
  Synplicity/Synopsys
• ECE 611 Advanced Microprocessors D. Tabak
• ECE 612 Real-Time Embedded Systems K. Hintz

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Concentration Area Advisors
DIGITAL SYSTEMS DESIGN Ken
Hintz
COMPUTER NETWORKS Brian
Mark
NETWORK AND SYSTEM SECURITY Kris Gaj
MICROPROCESSOR AND EMBEDDED SYSTEMS

Peter Pachowicz
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ECE 545
Projects
Lecture
Project 1 25 Project 2 10 Project 3 15
Homework 10
Midterm exams Midterm 1 20 in class
Midterm 2 20 take home
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Lecture (1)
Lecture 1 - Introduction to VHDL for
Synthesis Lecture 2 - Data Flow Structural
Modeling of Combinational
Logic. Packages and Components. Lecture 3
Behavioral Modeling of Sequential Logic.
Registers, Counters, Shift
Registers. Simple
Testbenches. Lecture 4 - Introduction to FPGA
Devices Tools Lecture 5 - Finite State
Machines Lecture 6 - Algorithmic State
Machines Lecture 7 Advanced Testbenches, File
I/O, Memory Lecture 8 - Mixed Style RTL
Modeling Lecture 9 - Advanced Examples Sorting,
Average, MAX, MIN Midterm 1
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Lecture (2)
Lecture 10 - Variables, Functions and
Procedures Lecture 11 ASIC Logic Synthesis with
Synopsys Design
Compiler Lecture 12 Advanced Data Types.
Operators and Attributes. Lecture 13 - Timing.
Event-Driven Simulation Lecture 14 - Behavioral
Modeling - The DLX Computer System Midterm Exam 2
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Textbooks
Required Textbooks Volnei A. Pedroni, Circuit
Design with VHDL, The MIT Press, 2004 Sundar
Rajan, Essential VHDL RTL Synthesis Done Right,
S G Publishing, 1998 Supplementary
Textbooks Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL Design,
2nd Edition, McGraw-Hill, 2005 Peter J.
Ashenden, The Designer's Guide to VHDL, 2nd
Edition, San FranciscoMorgan Kaufman, 1996, 2002
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Midterm exam 1

• 2 hours 30 minutes
• in class
• design-oriented
• open-books, open-notes
• practice exams will be available on the web

Tentative date
Wednesday, October 26th
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Midterm Exam 2

• take-home
• full design, including logic synthesis and
  timing analysis
• with Synopsys Design Compiler
• 48 hours

Tentative date
Saturday, Sunday, December 10-11
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Project technologies
FPGA Field Programmable Gate Arrays and ASIC
semi-custom Application Specific Integrated
Circuits
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World of Integrated Circuits
Integrated Circuits
Full-Custom ASICs
Semi-Custom ASICs
User Programmable
PLD
FPGA
PAL
PLA
PML
LUT (Look-Up Table)
MUX
Gates
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Two competing implementation approaches
FPGA Field Programmable Gate Array
ASIC Application Specific Integrated Circuit

• bought off the shelf
• and reconfigured by
• designers themselves

• designs must be sent
• for expensive and time
• consuming fabrication
• in semiconductor foundry

• no physical layout design
• design ends with
• a bitstream used
• to configure a device

• designed all the way
• from behavioral description
• to physical layout

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Which Way to Go?
ASICs
FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in high volumes
Reconfigurability
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What is an FPGA Chip ?

• Field Programmable Gate Array
• A chip that can be configured by user to
  implement different digital hardware
• Configurable Logic Blocks and Programmable Switch
  Matrices
• Bitstream to configure function of each block
  the interconnection between logic blocks

Source Brown99
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CLB Structure
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CLB Slice
COUT
YB
Look-Up Table
Carry Control Logic
Y
G4 G3 G2 G1
S
D
Q
O
CK
EC
R
F5IN
BY SR
XB
Look-Up Table
Carry Control Logic
X
S
F4 F3 F2 F1
D
Q
O
CK
EC
R
CIN CLK CE
SLICE
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LUT (Look-Up Table) Functionality

• Look-Up tables are primary elements for logic
  implementation
• Each LUT can implement any function of 4 inputs

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Major FPGA Vendors

• SRAM-based FPGAs
• Xilinx, Inc.
• Altera Corp.
• Atmel
• Lattice Semiconductor
• Flash antifuse FPGAs
• Actel Corp.
• Quick Logic Corp.

Share over 60 of the market
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Xilinx FPGA Families

• Old families
• XC3000, XC4000, XC5200
• old 0.5µm, 0.35µm and 0.25µm technology. Not
  recommended for modern designs.
• Low-cost families
• Spartan/XL derived from XC4000
• Spartan-II derived from Virtex
• Spartan-IIE derived from Virtex-E
• Spartan-3
• High-performance families
• Virtex (0.22µm)
• Virtex-E, Virtex-EM (0.18µm)
• Virtex-II, Virtex-II PRO (0.13µm)
• Virtex-4 (0.09µm)

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Design process (1)
Specification
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be
able to perform an encryption algorithm by
itself, executing 32 rounds..
VHDL description (Your VHDL Source Files)
Library IEEE use ieee.std_logic_1164.all use
ieee.std_logic_unsigned.all entity RC5_core is
port( clock, reset,
encr_decr in std_logic
data_input in std_logic_vector(31 downto 0)
data_output out std_logic_vector(31
downto 0) out_full in
std_logic key_input in
std_logic_vector(31 downto 0)
key_read out std_logic ) end
AES_core
Functional simulation
Synthesis
Post-synthesis simulation
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Design process (2)
Implementation (Mapping, Placing Routing)
Timing simulation
Configuration
On chip testing
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Design Process control from Active-HDL
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Simulation Tools

• Many others

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Logic Synthesis
VHDL description
Circuit netlist
architecture MLU_DATAFLOW of MLU is signal
A1STD_LOGIC signal B1STD_LOGIC signal
Y1STD_LOGIC signal MUX_0, MUX_1, MUX_2, MUX_3
STD_LOGIC begin A1ltA when (NEG_A'0')
else not A B1ltB when (NEG_B'0') else not
B YltY1 when (NEG_Y'0') else not
Y1 MUX_0ltA1 and B1 MUX_1ltA1 or
B1 MUX_2ltA1 xor B1 MUX_3ltA1 xnor
B1 with (L1 L0) select Y1ltMUX_0 when
"00", MUX_1 when "01", MUX_2 when
"10", MUX_3 when others end MLU_DATAFLOW
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Synthesis Tools

• and others

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Features of synthesis tools

• Interpret RTL code
• Produce synthesized circuit netlist in a standard
  EDIF format
• Give preliminary performance estimates
• Some can display circuit schematics corresponding
  to EDIF netlist

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Implementation

• After synthesis the entire implementation process
  is performed by FPGA vendor tools

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Mapping
LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
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Placing
FPGA
CLB SLICES
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Routing
FPGA
Programmable Connections
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Design Process control from Active-HDL
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Top Level ASIC Digital Design Flow
Design Inception
RTL Design
Synthesis
Macro Development
Place

Route
Physical Verification
Design Complete
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RTL Design
Design Function
Digital Tool
Design Inception
Design Inception
Cadence NC Verilog
RTL Design
Mentor Graphis ModelSim
Lint Checking
Cadence Hal
(
users discression)
FPGA Verification
Xilinx ISE
(
users discression)
Code Coverage
Cadence ICT
(
users discression)
Cadence NC Verilog
Testbench Developement
Mentor Graphics ModelSim
Mixed Mode Simulation
Cadence AMS Designer
Formal Verification
Cadence Conformal
Agilent ADS
System Interface Simulation
Matlab
Synthesis
Synthesis

Macro
Synthesis

Macro
Development
Development
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Synthesis Macro Development
Design Function
Digital Tool
RTL
RTL
Synopsys DC
Synthesis
Macro Generation
Artisan
Cadence RC
Synopsys DFT Compiler
DFT
Macro Verification
Mentor Graphics Calibre
Cadence RC
Artisan
/
Macro Rules Generation
/
Synopsys PrimeTime
Static Timing Analysis
Library Generation
Cadence DFII
Cadence Conformal
Logical Equivalency
Verification
Verification
Cadence NC Verilog
Gate
-
Level Simulation
Mentor Graphics Modelsim
Place

Route
Place

Route
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Place Route
Digital Tool
Design Function
Synthesis
Synthesis
Floorplan
Macro Placement
/
Std Cell
Placement
Cadence Encounter
Placement
-
Based
Optimization
Clock Tree Synthesis
Static
Synopsys
Timing
Prime
-
Analysis
Time
Route
Cadence NanoRoute
Spare Cells
/
Decoupling
Mentor Graphics
ATPG
Cap Filler Cells
FastScan
Cadence Encounter
RC Extraction
Cadence Fire

Ice QX
Signal Integrity
Cadence CeltIC
/
Voltage
Storm
Metal Fill
Cadence Encounter
Verification
Verification
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Physical Verification
Digital Tool
Design Function
Placed

Routed
Placed

Routed
Design
Design
GDSII Preparation
/
Simulation Preparation
Cadence DFII
Cadence DFII
Schematic Preparation
Back Annotated Simulation
Layout
Chip Finishing
Cadence NC Verilog
Cadence Virtuoso
DRC
LVS
Mentor Graphics Calibre
ERC
Synopsys Nanosim
Top
-
Level Simulation
Cadence AMS Designer
Design Complete
Design Complete
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CAD software available at GMU (1)
VHDL simulators

• Aldec Active-HDL (under Windows)

• available in the FPGA Lab, ST II, room 203

• student edition can be purchased on an
  individual
• basis (59.95 SH)

• ModelSim (under Unix)

• available from all PCs in the ECE educational
  labs
• using an X-terminal emulator
• available remotely from home using a fast
  Internet
• connection

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CAD software available at GMU (2)
Tools used for logic synthesis
FPGA synthesis

• Synplicity Synplify Pro (under Windows)

• Xilinx XST (under Windows)

• available in the FPGA Lab, ST II, room 203

ASIC synthesis

• Synopsys Design Compiler (under Unix)

• available from all PCs in the ECE educational
  labs
• using an X-terminal emulator
• available remotely from home using a fast
  Internet
• connection

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CAD software available at GMU (3)
Tools used for implementation (mapping, placing
routing) in the FPGA technology

• Xilinx ISE (under Windows)

• available in the FPGA Lab, ST II, room 203

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Projects Overview
Project 1 (25 points) mid-September October
(6 weeks)
Application cryptography OR digital signal
processing Technology FPGA Target
synthesizable code, timing, resource usage
Project 2 (10 points) November (3 weeks)
Application the same as in Project
1 Technology ASIC Target
revised synthesizable code, synthesis scripts,
timing, resource usage,
comparison
Project 3 (15 points) December (3 weeks)
Application simple microprocessor/microcontrol
ler Target behavioral code
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Projects 1, 2

• choice between two project topics
• cryptography (e.g., encryption, authentication,
  hash)
• digital signal processing (e.g., digital filter,
  FFT,
• 
  image processing, etc.)
• both topics specified by the instructor
• initial specification in the form of a
• - pseudocode and/or flowchart
• - detailed interface
• design and source code is required to be
  scalable,
• i.e., work for different parameters and
  operand sizes,
• specified at the time of synthesis

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Example Last years project - RC5 cipher
Decryption
Encryption
A B C for i r downto 1 do B
((B?S2i1) gtgtgt A) ? A A ((A ? S2i)gtgtgtB) ?
B B B ? S1 A A ? S0 M A B
A B M A A S0 B B S1 for i 1
to r do A (A?B) ltltlt B S2i B (B?A)
ltltlt A S2i1 C A B
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clock
Encryption/decryption unit
reset
encrypt/decrypt
data output
m
n
data input
write
data available
full
data read
round number
round key(s)
Key memory
round key(s)
cycle number
k
key input
Key scheduling unit
key available
key read
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Projects 1, 2Optimization Criteria

• Maximum ratio
• Throughput / Circuit Area
• or
• Minimum product
• Latency ? Circuit Area

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Primary timing parameters
Latency
Throughput
Xi2
Xi
Xi1
Xi
Time to process a single block of data
Circuit
Circuit
Number of bits processed in a unit of time
Yi2
Yi
Yi1
Yi
Block_size Number_of_blocks_processed_simultaneo
usly
Throughput
Latency
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Project 3from FALL 2004to be modified in FALL
2005
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System to be implemented

• Using high-level behavioral VHDL describe
• an 8-bit microcontroller MC68HC11E9, working
• in a single-chip mode, with the following
• simplifications
• Inputs and outputs of the microcontroller are
  reduced to
• clk, reset, PORTB, and PORTC.
• Internal registers are reduced to the registers
• A, B, SP, CC (Condition Codes NZVC), and PC.
• Internal I/O registers are limited to
• PORTB at the memory address 1004
• PORTC at the memory address 1003
• DDRC at the memory address 1007

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• 4. Instruction set of the microcontroller is
  reduced
• to the following instructions
• Data transfer instructions
• LDAA, LDAB, LDS, STAA, STAB, STS
• Arithmetic instructions
• ADDA, ADDB, SUBA, SUBB
• Logic instructions
• ANDA, ANDB, ORAA, ORAB, EORA, EORB
• Data test instructions
• CMPA, CMPB
• Control instructions
• BEQ, BNE, BSR, RTS
• Stack instructions
• PSHA, PSHB, PULA, PULB

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5. Addressing modes of the microcontroller are
reduced to the following modes a.
immediate b. extended c. inherent d.
relative 6. Program is stored in the internal ROM
starting at the address D000 7. After
reset, PC is set to the address D000. 8. The
only parts of 68HC11E9 implemented in your
model are a. CPU b. RAM (512 B in the range
0000-01FF) c. ROM (12 kB in the range
D000-FFFF) d. parallel I/O (PORTB and PORTC)
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Features of the model

• Your model should allow cycle accurate modeling
• of the circuit behavior.
• 2. Your model should contain debugging features
• equivalent to the debugging features of the DLX
  model,
• discussed in class and described in Ashenden,
  Chapter 15.
• 3. Generic parameters passed to the model
• should include
• a. name of the file with the contents of the
  internal ROM
• b. clk-to-output delay
• c. debugging mode
• Your model should report all undefined opcodes,
• treat them as NOP, and proceed to the next ROM
  address.

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Testing and debugging
The behavior of your model should be carefully
verified using a testbench instantiating your
model with a. the internal ROM containing a
valid program composed of a substantial
subset of instructions implemented in the
model b. debugging mode set to the most detailed
mode (trace_each_step)
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Deliverables

• All source code files.
• Contents of the internal ROM used for
• the model verification, in the hexadecimal
  notation, and
• expressed using the corresponding 68HC11
• assembly language mnemonics.
• The detailed log/report generated by your model
• for a given contents of ROM, and with the
  debugging
• mode set to trace_each_step.

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All Projects - Organization

• Projects divided into phases
• Intermediate code submitted through WebCT at
  selected checkpoints and evaluated by the
  instructor and/or TA
• Penalty points for falling behind the schedule
  (below 50 of the work that supposed to be done
  by a certain deadline)
• Feedback provided to students on a fair and best
  effort basis
• Final report and codes submitted by WebCT and
  graded using a full scale
• Contest for the best results (bonus points
  awarded to the winners)
• Penalty and bonus points added to the final grade

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Honor Code Rules

• All students are expected to write and debug
  their codes individually
• Students are encouraged to help and support each
  other in all problems related to the- operation
  of the CAD tools,- basic understanding of the
  problem.