Timing Analysis

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Timing Analysis
Chaitanya Bandi
Instructor Dr. Vishwani D. Agrawal
ELEC 7770 Advanced VLSI
Design Team Project
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Need for Timing Analysis

• High-performance integrated circuits have
  traditionally been characterized by the clock
  frequency at which they operate.
• While timing measurements can theoretically be
  performed using a rigorous circuit simulation,
  such an approach is liable to be too slow to be
  practical.

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Primitive device delay models

• A primitive logic gate has an intrinsic delay.

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Methods of Timing Analysis

• Static Timing analysis after Synthesis
  (Pre-Layout Analysis)
• Static Timing analysis after Place and Route
  (also called as Post-Layout Analysis)

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Static Timing Analysis

• Only two kinds of timing errors are possible
  in such a system
• A hold time violation, when a signal arrives too
  early, and advances one clock cycle before it
  should.
• A setup time violation, when a signal arrives too
  late, and misses the time when it should advance.

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Area Optimized Vs Delay Optimized

• From the Synthesis report of the Area and
  Delay Optimized versions, the Area Optimized
  version has lesser Area and Delay compared to the
  Delay Optimized version.

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Tools to perform Timing Analysis

• QuickSim
• Mach TA
• Eldo
• Leonardo (Results from the Synthesis)

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ELDO Design Flow
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Procedure

• Extract the schematic from the Netlist.
• Export it as a Spice format.
• Force vectors to observe the critical path from
  the simulation results files.
• Find the critical path from the Waveform Viewer
  (EZWAVE)

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Leonardo

• The Delays from the Area Optimized netlist shows
  that the CPU design has a critical path that has
  a delay of 13.13ns
• This is just an estimate of the pre-layout timing
  analysis. This delay may differ based on the
  level of optimization.

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Further Work

• The Post layout incorporates both the block and
  routing delays as a final analysis of the
  designs timing constraints.
• Post layout simulation is a better parameter to
  find the maximum operational frequency and
  behavior of the circuit.

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Mach TA Post Layout Design
Flow
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Questions??

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Suggestions

• Technology that is supported by the timing
  analysers.
• 32-bit Processor requires simulation of few days
  to perform the timing and power analysis. A
  16-bit processor would have been a better choice.