NS9750%20-%20Training%20%20Hardware

1
NS9750 - Training Hardware
2
NS9750 System Overview
3
NS9750 - A NETARM Processor The highest
performance Network Attached processor available
in the market

• The most advanced ARM9 processor
• Rich set of components peripherals
• Deterministic performance
• Low latency

4
NS9750352-pin, 35mm X 35mm BGA, 35mmx35mm,
1.27mm pitch
5
Mercury System Overview

• Two Internal System Buses
• Main System Bus 100 MHz AHB Bus
• Peripheral Bus 50 MHz B-Bus
• Two External Buses
• 100 MHz Memory Bus Supports SDRAM, FLASH, SRAM,
  Peripheral w/ SRAM interface
• 33 MHz PCI Bus Supports 3 external PCI devices

6
Mercury System Overview

• System Block Diagram

7
System Block Diagram
8
Mercury System Overview

• Main System Bus Components
• CPU 200 MHz ARM 926EJ-S, Master
• Ethernet Controller w/o PHY, Master/Slave
• Color LCD Controller, Master/Slave
• PCI Host/Device Bridge, Master/Slave
• B-Bus Bridge, Master/Slave
• Color Laser Printer Controller, Master/Slave
• Memory Controller, Slave Only

9
Mercury System Overview

• Main System Bus Utilities
• System Clock Generation
• System Control Timers and General Purpose Timers
• Prioritized Vectored Interrupt Controller
• Bus Bandwidth Configurable Bus Arbiter
• System Sleep/Wake-up Processor

10
Mercury System Overview

• Peripheral Bus Components
• USB Host/Device 1.5 Mbytes/sec.
• I2C Controller 400Kbits/sec.
• Clock Stretching , Bus Arbitration.
• IEEE1284 Device Interface 1MBytes/sec.
• Serial Module 4 Independent Ports, Software
  selectable UART (Standard Rates), HDLC (6
  Mbits/sec.), SPI (6Mbits/sec.)
• GPIO

11
Mercury System Overview

• Peripheral Bus Utilities
• DMA Controller
• Bus Monitor Timers

12
Mercury System Performance

• System Performance is Memory Centric
• Operating Frequencies
• Memory System Throughput
• Data Bandwidth Allocation
• Interrupt Latency
• Power Consumption

13
Mercury System Performance

• Operating Frequencies
• CPU 200 MHz
• All AHB Bus Components 100 MHz
• Printer Data Clock 100 MHz
• All B-Bus Components 50 MHz
• USB 12 Mbits/sec.
• Async Serial Comm Standard Rates up to 1.9
  Mbits/sec
• Sync Serial Comm up to 6 Mbits/sec

14
Mercury System Performance

• Memory System (SDRAM) Performance
• Worstcase Data Bandwidth 200 Mbytes/sec. Burst
  of 8 Access
• Average Data Bandwidth 230 Mbytes/sec. Burst of
  8 Access
• 50 Bandwidth Prioritized to CPU
• 50 Bandwidth Prioritized to all other AHB
  Masters
• Bandwidth Allocation Controlled by AHB Bus
  Arbiter

15
Mercury System Performance

• Guaranteed Data Bandwidth Allocation
• Worstcase Bandwidth Calculation Formula
• (100Mclks / 2) / (16clks X of non-CPU masters)
  X 32 Bytes/sec X of slots occupied
• Total Of 16 non-CPU Master Slots
• A Master Can Occupy More Than One Slot
• A Master Can Occupy a Fraction of One Slot
• A Master May Occupy No Slot (disabled)

16
Mercury System Performance

• Interrupt Latency
• Latency is measured from Interrupt Assertion to
  the execution of the 1st instruction of the ISR
• Latency Calculation Formula
• Clks of current instruction clks of reading
  interrupt vector clks of jump to top level IRS
  clks of parse thru interrupt sources clks of
  jump to final ISR
• Total Of 32 Interrupt Vectors (entries) to
  minimize of interrupt sources per vector
• Deterministic Interrupt Latency Achievable

17
Mercury System Performance

• Power Consumption

18
ARM 926EJ-S CPU

• Reduced Instruction Set Computer (RISC)
• Five-Stage Pipe Line
• Harvard Architecture
• 8K I-Cache, 4K D-Cache
• Memory Management Unit
• JAVA Accelerator
• DSP Extension
• Thumb Mode

19
ARM 926EJ-S CPU

• Reduced Instruction Set
• 32-bit ARM Instructions is a superset of 16-bit
  Thumb Instructions
• 32-bit ARM Instructions
• Move, Arithmetic, Logical, Branch, Load, Store,
  Cache Hint, Swap, Software Interrupt, Software
  Breakpoint
• 16-bit Thumb Instructions
• Move, Arithmetic, Logical, Shift/Rotate, Branch,
  Load, Store, Push/Pop, Software Interrupt,
  Software Breakpoint.
• Thumb mode has Full 32-bit register advantage

20
ARM 926EJ-S CPU

• Five Stage Pipe Line

21
ARM 926EJ-S CPU

• Harvard Architecture
• Separated Data and Instruction Path
• Separated Data and Instruction Cache
• Balanced CPU access to data and instructions
  benefits the most
• Example DSP Processor

22
ARM 926EJ-S CPU

• 8K I-Cache, 4K D-Cache
• 4-Way Set Associative Cache
• D-Cache Write-Thru mode is recommended due to no
  bus snooping
• Programmable Pseudo-random or Round-Robin
  Replacement
• Write buffer to improve system performance

23
ARM 926EJ-S CPU

• Memory Management Unit
• Required by Symbian OS, WindowsCE, and Linux
• Two level page tables in main memory to control
• Address translation
• Permission checks
• Memory region attributes
• Use Translation Lookaside Buffer (TLB) to cache
  page tables
• TLB entries can be locked down

24
ARM 926EJ-S CPU

• JAVA Accelerator
• Efficient JAVA Byte Code Execution
• Similar JAVA performance to JIT w/o associated
  code overhead

25
ARM 926EJ-S CPU

• DSP Extension
• Combines system control and signal processing
  (DSP) into one processor.
• Intel has adopted ARMs DSP extension in their
  Xscale Microarchitecture.
• New powerful Multiply instructions
• New Saturation extension for stable control loops
  and bit-exact algorithm
• Cache Preload instruction
• New instructions to load and store pairs of
  registers.

26
ARM 926EJ-S CPU

• Thumb Mode
• 16-bit instruction set improves Code Density
• Thumb code is typically 65 of the size of ARM
  code
• Full 32-bit register advantage
• Interchangeable with ARM mode dynamically
• All exception handlings are in ARM mode
• Power up in ARM mode

27
System Boot

• Low cost boot from serial EEPROM through SPI port
• High speed boot from 8-bit, 16-bit, or 32-bit ROM
  or Flash