NS9750%20-%20Training%20%20Hardware

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NS9750 - Training Hardware
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1284
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Traffic Flow
Note Traffic direction in the 1284 is classified
as either forward or reverse. The forward
direction is equivalent to NS9750 Receive.
Likewise, the reverse direction is equivalent to
NS9750 Transmit.
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1284 Overview

• Provides asynchronous and bi-directional parallel
  communications between a PC, or other host, and a
  printer.
• NS9750 supported 1284 modes Compatibility,
  Nibble, Byte, ECP.
• NS9750 operates as a slave (peripheral) device
  only.
• Compatibility
• A byte-wide single direction connection from the
  host to the peripheral.
• The default mode of operation.
• Backwards compatible with many existing devices.
• Nibble
• A nibble-wide single direction connection from
  the peripheral to the host.

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1284 Overview

• Byte
• A byte-wide single direction connection from the
  peripheral to the host.
• ECP
• A byte-wide bi-directional connection between the
  host and peripheral.
• Distinguishes between command and data transfers.
• More efficient, but more complex, method of
  sharing data than using either a (compatibility
  nibble) or (compatibility byte) combination.
• Note
• No need for a user to use both nibble and byte
  modes.
• The byte mode is slightly less complicated to
  use.

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Modes of Operation

• Two primary modes of communications between the
  1284 and the rest of the chip (DMA CPU).
• DMA
• Establish 4 DMA channels in the BBUS DMA
  Controller. These channels connect directly to
  the four primary FIFOs.
• Ch9 (FWD CMD) 10 (REV CMD) 11 (FWD DATA) 12
  (REV DATA)
• Allocate corresponding channel buffers
• Configure corresponding control registers
• Not an interrupt driven data flow between the
  1284 and the BBUS.
• Can mask all the interrupts in the Status and
  Control Register
• Can limit the size of receive (forward) DMA
  buffers. (DMA Control Reg)
• Recommended for most customers.
• Provides a more powerful and higher performance
  interface into the 1284.

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Modes of Operation

• CPU
• The CPU can directly access the 4 primary FIFOs .
• FIFO locations are located at addresses
  (0x9040_000C 0x9040_0020)
• The CPU requires the use of interrupts to move
  data through the interface.
• Requires more polling of the FIFOs to ensure that
  they do not overrun / underrun. The DMA can
  handle this automatically.
• Recommended for debug purposes.
• Requires less configuration work in the rest of
  the chip.
• Does require a more intimate knowledge of
  incoming data in order to set appropriate
  thresholds for interrupt triggerable events.

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1284 Sample Initialization

• Bbus Utility block
• Clear the Bbus Utility and 1284 module reset
  (Master Reset)
• Configure GPIO pins (GPIO Configuration
  Registers)
• Bbus Bridge block
• Enable layered interrupts (Bbus Bridge Interrupt
  Enable)
• 1284
• Set 1284 pins to 1 before initialization (Port
  Control)
• Set general user settings (General Configuration)
• Clear any spurious received interrupts (Interrupt
  Status Control)
• Set appropriate interrupt mask bits (Interrupt
  Status Control)
• Set Fwd. Data/CMD Max Buffer size byte gap time
• CPU Mode -gt set Max buffer to 16hFFFF (Fwd. DMA
  Control)

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1284 Sample Initialization

• 1284 (cont)
• Set Port Granularity to 1 initially before
  configuring the registers. Set to 0x19 before
  traffic flow. (Granularity)
• Set buffer for reverse ID transfers (Feature b)
• Set Negotiation Start detect int enable
  (Interrupt Enable)
• Disable open drain. Enable reverse request.
  (Extended Control)
• Set Buffer Thresholds. Enable printer port.
  (Feature A)
• Enable desired features (Master Enable)

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1284 Timing
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Hints Kinks

• Which interrupts are essential even in DMA mode?
• VCM1 (Interrupt Status Control) is an aggregate
  of 1284 core interrupts
• Negotiation Start (STI) indicates a new transfer
  mode has begun.
• Pin Select (STI) is an aggregate of the PIT
  register.
• N_init edge detect (PIT) indicates that data flow
  has reversed in ECP mode.
• How can I figure out which is the active data
  transfer mode?
• When negotiating into a new mode the IEEE 1284
  Extensibility Value is placed on the data line.
  This value identifies the mode. It is important
  to note that compatability mode does not have
  such a value. This is because it is the default
  mode. Therefore, the 1284 is in compatability
  mode when it is not in another mode. It should
  also be pointed out the 1284 cannot negotiate
  into a mode except from compatability mode.

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Hints Kinks

• How is traffic classified as either data or
  command?
• During an ECP transfer a value of 1 on the
  HostAck (nAutoFd) wire indicates a data transfer.
  A 0 indicates a command transfer.
• So what exactly is command traffic anyway?
• There are two possible commands that can be sent
  run-length encoding (rle) compression and channel
  address. Bit 7 of the command is used to select
  the type of command. ( 0 -gt compression 1 -gt
  channel address)
• Rle Compression The next byte is repeated (bits
  60 1) times and put in the appropriate FIFO.
  Note The user must make sure that the next byte
  transferred is classified as data in order for it
  to replicated in the data FIFO.
• Channel Address Bits 60 of the current byte
  are stored as a channel address which can be read
  in the ECA register.
• What are other sources of information?
• www.ieee.org Standards 1284-1994.
• NS9775 users manual.