Embedded%20Hardware%20Foundation

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Embedded Hardware Foundation
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Content

• CPU
• Bus
• Memory
• I/O
• Design, develop and debug

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1. CPU

• I/O programming
• Busy/wait
• Interrupt-driven
• Supervisor mode, exceptions, traps
• Co-processor
• Memory System
• Cache
• Memory management
• Performance and power consumption

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I/O devices

• Usually includes some non-digital component.
• Typical digital interface to CPU

status reg
CPU
mechanism
data reg
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Application 8251 UART

• Universal asynchronous receiver transmitter
  (UART) provides serial communication.
• 8251 functions are integrated into standard PC
  interface chip.
• Allows many communication parameters to be
  programmed.

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8251 CPU interface
8251
status (8 bit)
CPU
xmit/ rcv
data (8 bit)
serial port
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Programming I/O

• Two types of instructions can support I/O
• special-purpose I/O instructions
• memory-mapped load/store instructions.
• Intel x86 provides in, out instructions. Most
  other CPUs use memory-mapped I/O.
• I/O instructions do not preclude memory-mapped
  I/O.

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ARM memory-mapped I/O

• Define location for device
• DEV1 EQU 0x1000
• Read/write code
• LDR r1,DEV1 set up device address
• LDR r0,r1 read DEV1
• LDR r0,8 set up value to write
• STR r0,r1 write value to device

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peek and poke (Using C)

• int peek(char location)
• return location
• void poke(char location, char newval)
• (location) newval

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Busy/wait output

• Simplest way to program device.
• Use instructions to test when device is ready.
• char mystring"hello, world."
• char current_char
• current_char mystring
• while (current_char ! \0)
• while (peek(OUT_STATUS) ! 0)
• poke(OUT_CHAR,current_char)
• current_char

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Simultaneous busy/wait input and output

• while (TRUE)
• / read /
• while (peek(IN_STATUS) ! 0)
• achar (char)peek(IN_DATA)
• / write /
• while (peek(OUT_STATUS) ! 0)
• poke(OUT_DATA,achar)

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Interrupt I/O

• Busy/wait is very inefficient.
• CPU cant do other work while testing device.
• Hard to do simultaneous I/O.
• Interrupts allow a device to change the flow of
  control in the CPU.
• Causes subroutine call to handle device.

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Interrupt interface
intr request
status reg
CPU
intr ack
mechanism
PC
IR
data/address
data reg
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Interrupt behavior

• Based on subroutine call mechanism.
• Interrupt forces next instruction to be a
  subroutine call to a predetermined location.
• Return address is saved to resume executing
  foreground program.

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Interrupt physical interface

• CPU and device are connected by CPU bus.
• CPU and device handshake
• device asserts interrupt request
• CPU asserts interrupt acknowledge when it can
  handle the interrupt.

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Example interrupt-driven input and output

• void input_handler()
• void output_handler()
• main()
• while (TRUE)
• if (gotchar)
• while (peek(OUT_STATUS) ! 0)
• poke(OUT_DATA,achar)
• gotchar FALSE

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Example character I/O handlers

• void input_handler()
• achar peek(IN_DATA)
• gotchar TRUE
• poke(IN_STATUS,0)
• void output_handler()

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Example interrupt I/O with buffers

• Queue for characters

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Buffer-based input handler

• void input_handler()
• char achar
• if (full_buffer())
• error 1
• else
• achar peek(IN_DATA)
• add_char(achar)
• if (nchars 1)
• poke(OUT_DATA,remove_char()
• poke(OUT_STATUS,1)

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Buffer-based output handler

• void output_handler()
• if (!empty_buffer())
• poke(OUT_DATA, remove_char())
• / send character /
• poke(OUT_STATUS, 1)
• /turn device on /

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Priorities and vectors

• Two mechanisms allow us to make interrupts more
  specific
• Priorities determine what interrupt gets CPU
  first.
• Vectors determine what code is called for each
  type of interrupt.
• Mechanisms are orthogonal most CPUs provide both.

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Prioritized interrupts
device 1
device 2
device n
interrupt acknowledge
CPU
L1 L2 .. Ln
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Interrupt prioritization

• Masking interrupt with priority lower than
  current priority is not recognized until pending
  interrupt is complete.
• Non-maskable interrupt (NMI) highest-priority,
  never masked.
• Often used for power-down.

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Interrupt vectors

• Allow different devices to be handled by
  different code.
• Interrupt vector table

Interrupt vector table head
handler 0
handler 1
handler 2
handler 3
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Interrupt vector acquisition
device
interruput request
interruput ack.
vector
CPU
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Interrupt vector acquisition
CPU
device
receive request
receive ack
receive vector
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Interrupt sequence

• CPU checks pending interrupt requests and
  acknowledges the one of highest priority.
• Device receives acknowledgement and sends vector.
• CPU locates the handler using vector as index of
  interrupt table and calls the handler.
• Software processes request.
• CPU restores state to foreground program.

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Sources of interrupt overhead

• Handler execution time.
• Interrupt mechanism overhead.
• Register save/restore.
• Pipeline-related penalties.
• Cache-related penalties.

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ARM interrupts

• ARM7 supports two types of interrupts
• Fast interrupt requests (FIQs).
• Interrupt requests (IRQs).
• Interrupt table starts at location 0.

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ARM interrupt procedure

• CPU actions
• Save PC. Copy CPSR to SPSR.
• Force bits in CPSR to record interrupt.
• Force PC to vector.
• Handler responsibilities
• Restore proper PC.
• Restore CPSR from SPSR.
• Clear interrupt disable flags.

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Exception and Trap

• Exception
• internally detected error.
• Exceptions are synchronous with instructions but
  unpredictable.
• Build exception mechanism on top of interrupt
  mechanism.
• Exceptions are usually prioritized and
  vectorized.
• Trap (software interrupt)
• an exception generated by an instruction.
• Call supervisor mode.

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Supervisor mode

• May want to provide protective barriers between
  programs.
• Avoid memory corruption.
• Need supervisor mode to manage the various
  programs.

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ARM CPU modes
????? ??
????(User, usr) ?????????
??????(FIQ, fiq) ?????????????
??????(IRQ, irq) ?????????
????(Supervisor, svc) ??????????????
???????? (Abort, abt) ???????????
????????? (Undefined, und) ?????????????????
???? ??????????????
????
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ARM CPU modes (contd)

• SWI (Software interrupt)??
• ??
• SWIlt???gt immed_24
• SWI??????????,?????????, CPSR????????SPSR?,????0x0
  8???????ltimmed_24gt???????

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Co-processor

• Co-processor added function unit that is called
  by instruction.
• Floating-point units are often structured as
  co-processors.
• ARM allows up to 16 designer-selected
  co-processors.
• Floating-point co-processor uses units 1 and 2.

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Memory System

• Cache
• Memory Management Unit

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Cache

• Small amount of fast memory
• Sits between normal main memory and CPU
• May be located on CPU chip or module

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Cache operation - overview

• CPU requests contents of memory location
• Check cache for this data
• If present, get from cache (fast)
• If not present, read required block from main
  memory to cache
• Then deliver from cache to CPU
• Cache includes tags to identify which block of
  main memory is in each cache slot

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Cache operation

• Many main memory locations are mapped onto one
  cache entry.
• May have caches for
• instructions
• data
• data instructions (unified).
• Memory access time is no longer deterministic.

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Cache organizations

• Direct-mapped each memory location maps onto
  exactly one cache entry.
• Fully-associative any memory location can be
  stored anywhere in the cache (almost never
  implemented).
• N-way set-associative each memory location can
  go into one of n sets.

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Example

• Cache of 64kByte
• Cache block of 4 bytes
• i.e. cache is 16k (214) lines of 4 bytes
• 16MBytes main memory
• 24 bit address (22416M)
• 222 blocks 28 blocks will be mapped into one
  cache line on the average

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Direct-mapped cache

• Each block of main memory maps to only one cache
  line
• i.e. if a block is in cache, it must be in one
  specific place
• Address is in two parts
• Least Significant w bits identify unique word
• Most Significant s bits specify one memory block
• The MSBs are split into a cache line field r and
  a tag of s-r (most significant)

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Direct MappingAddress Structure
Line or Slot r
Word w
Tag s-r
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2
8

• 24 bit address
• 2 bit word identifier (4 byte block)
• 22 bit block identifier
• 8 bit tag (22-14)
• 14 bit slot or line
• No two blocks in the same line have the same Tag
  field
• Check contents of cache by finding line and
  checking Tag

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Direct-mapped cache
valid
tag
data
cache block
tag
index
offset

value
hit
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• Fully-associative cache
• Set-associative cache

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Write operations

• Write-through immediately copy write to main
  memory.
• Write-back write to main memory only when
  location is removed from cache.

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Memory management units

• Memory management unit (MMU) translates addresses

main memory
logical address
memory management unit
physical address
CPU
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Memory management tasks

• Allows programs to move in physical memory during
  execution.
• Allows virtual memory
• memory images kept in secondary storage
• images returned to main memory on demand during
  execution.
• Page fault request for location not resident in
  memory.

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Address translation

• Requires some sort of register/table to allow
  arbitrary mappings of logical to physical
  addresses.
• Two basic schemes
• segmented
• paged.
• Segmentation and paging can be combined (x86).

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Segments and pages
memory
segment 1
page 1
page 2
segment 2
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Segment address translation
segment base address
logical address

range error
segment lower bound
range check
segment upper bound
physical address
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Page address translation
page
offset
page i base
concatenate
page
offset
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Page table organizations
page descriptor
page descriptor
flat
tree
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Caching address translations

• Large translation tables require main memory
  access.
• TLB cache for address translation.
• Typically small.

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ARM memory management

• Memory region types
• section 1 Mbyte block
• large page 64 kbytes
• small page 4 kbytes.
• An address is marked as section-mapped or
  page-mapped.
• Two-level translation scheme.

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CPU performance and power consumption
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Example Intel XScale core
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2. Bus

• ??CPU????????????
• ????????
• ????????
• ???????
• ?????
• ?????????,?CPU,DMA???

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?????????
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DMA

• DMA Direct Memory Access
• ??????CPU????????DMA???DMA?????,??CPU?????????????
  ,DMA????????????????????

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?DMA????????

• ???????
• ????
• ????

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?

• ?????????
• ????
• ?????????????
• ????????
• ???????????I/O????????

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ARM??-AMBA

• AMBA Advanced Microcontroller Bus Architecture
• 2.0?AMBA?????????
• AHB(AMBA High-performance Bus)
• ASB(AMBA System Bus)
• APB(AMBA Peripheral Bus)

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?????AMBA???

• ???????AMBA????????AHB?ASB??,???APB???
• ASB???????????AHB????,???????????????????

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3. Memory

• RAM
• SRAM
• DRAM
• ROM
• PROM,EPROM,EEPROM
• Flash ROM
• Flash????????????(boot ROM?hard disk)

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4. I/O

• Watchdog timer
• A/D D/A Converter
• LCD
• LED
• Touch screen
• Key board
• USB

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Watchdog timer

• ???????????????????????????????????????????
• ?????????,????????????????????????????,???????????
  ?????????????,???????????,????????,????,?????CPU??
  ?

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Watchdog timer

• Watchdog timer is periodically reset by system
  timer.
• If watchdog is not reset, it generates an
  interrupt to reset the host.

host CPU
interrupt
watchdog timer
reset