Verilog Modules for Common Digital Functions

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Verilog Modules for Common Digital Functions
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Full Adder (Dataflow Description)
// // Here is a data flow description of a
full_adder // module fa(sum, co, a, b, ci)
output sum, co input a, b, ci
assign sum a b ci assign co (a
b) ((a b) ci) endmodule
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Full Adder (Behvioral Description)
// 1-bit full-adder (behavioral) module fa(sum,
co, a, b, ci) input a, b, ci output
co, sum assign co, sum a b ci
endmodule
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Full Adder Testbench
// testbench for fa cell module fa_tb reg
a, b, ci reg 30 i wire sum, co
fa u0(sum, co, a, b, ci) initial
begin monitor(time, " a is b, b is b,
ci is b, sum is b, co is b\n", a, b, ci,
sum , co) for (i0 i lt 8 ii1) 10
a, b, ci i end endmodule
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Adder (4-bit) Structural Description
// Module to implement a 4-bit adder //
Structural description using fa module module
adder4(sum, co, a, b, ci) output 30 sum
output co input 30 a input
30 b input ci wire 31 c
fa g0(sum0, c1, a0, b0, ci) fa
g1(sum1, c2, a1, b1, c1) fa
g2(sum2, c3, a2, b2, c2) fa
g3(sum3, co, a3, b3, c3) endmodule
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2-1 Multiplexer
// 2-1 MUX // This is a behavioral
description. module mux2to1(out, sel, in)
input sel output out input 10 in
reg out always _at_(sel or in) begin
if (sel 1) out in1 else out
in0 end endmodule
// This is a dataflow description module
mux2to1(out, sel, in) input sel output
out input 10 in assign out sel
? in1 in0 endmodule
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2-1 Multiplexer (Case Statement)
// 2-1 MUX // This is a behavioral
description. module mux2to1(out, sel, in)
input sel output out input 10 in
reg out always _at_(sel or in) begin
case (sel) 0 out in0 1
out in1 endcase end endmodule
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3-8 Decoder
// // 3-8 decoder with an enable input //
This is a behavioral description. // module
decoder(out, en, a) output 70 out
input 20 a input en reg
70 out always _at_(a or en) begin out
8'd0 case(a) 3'd0 out 8'd1
3'd1 out 8'd2 3'd2 out 8'd4
3'd3 out 8'd8 3'd4 out 8'd16
3'd5 out 8'd32 3'd6 out 8'd64
3'd7 out 8'd128 default display("The
unthinkable has happened.\n") endcase
if (!en) out 8'd0 end endmodule
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3-8 Decoder Testbench
// Test bench for 3-8 decoder module decoder_tb
reg 20 a reg en reg
30 i wire 70 out // Instantiate
the 3-8 decoder decoder uut(out, en,
a) // Exhaustively test it initial begin
monitor(time, " en is b, a is b, out is
b\n",en, a, out) 10 begin
en 0 for (i0 i lt 8 ii1) 10 a i
end 10 begin en
1 for (i0 i lt 8 ii1) begin 10 a
i end end endmodule
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Digital Magnitude Comparator
// 4-bit magnitude comparator // This is a
behavioral description. module magcomp(AltB,
AgtB, AeqB, A, B) input 30 A, B
output AltB, AgtB, AeqB assign AltB (A lt
B) assign AgtB (A gt B) assign AeqB
(A B) endmodule
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D-Latch
/ Verilog description of a negative-level
senstive D latch with preset (active
low) / module dlatch(q, clock, preset, d)
output q input clock, d, preset
reg q always _at_(clock or d or preset)
begin if (!preset) q 1 else if
(!clock) q d end endmodule
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D Flip Flop
// Negative edge-triggered D FF with sync
clear module D_FF(q, d, clr, clk) output
q input d, clr, clk reg q
always _at_ (negedge clk) begin if
(clr) q lt 1'b0 else
q lt d end endmodule
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D Flip Flop Testbench
// Testbench for D flip flop module test_dff
wire q reg d, clr, clk
D_FF u0(q, d, clr, clk) initial
begin clk 1'b1 forever 5 clk
clk end initial fork 0
begin clr 1'b1 d
1'b0 end 20 begin
d 1'b0 clr1'b0
end 30 d 1'b1 50 d 1'b0
join initial begin
monitor(time, "clrb, db,qb", clr, d, q)
end endmodule
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4-bit D Register with Parallel Load
// // 4-bit D register with parallel
load // module dreg_pld(Dout, Din, ld, clk)
input 30 Din input ld, clk
output 30 Dout reg 30 Dout
always _at_(posedge clk) begin if (ld) Dout lt
Din else Dout lt Dout end endmodule
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1-Bit Counter Cell
// 1 bit counter module module cnt1bit(q, tout,
tin, clr, clk) output q output tout
input tin input clr input
clk reg q assign tout tin q
always _at_ (posedge clk) begin if
(clr 1'b1) q lt 0 else if
(tin 1'b1) q lt q end
endmodule
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2-Bit Counter
// 2-bit counter module cnt2bit(cnt, tout,
encnt, clr, clk) output 10 cnt
output tout input encnt input
clr input clk wire ttemp
cnt1bit u0(cnt0, ttemp, encnt, clr, clk)
cnt1bit u1(cnt1, tout, ttemp, clr, clk)
endmodule
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74161 Operation
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4-bit Synchronous Counter (74LS161)
// 4-bit counter module counter_4bit(clk, nclr,
nload, ent, enp, rco, count, parallel_in)
input clk input nclr input nload
input ent input enp output rco
output 30 count input 30 parallel_in
reg 30 count reg rco
always _at_ (count or ent) if ((count 15)
(ent 1'b1)) rco 1'b1 else rco
1'b0 always _at_ (posedge clk or
negedge nclr) begin if (nclr 1'b0)
count lt 4'd0 else if (nload
1'b0) count lt parallel_in else
if ((ent 1'b1) (enp 1'b1))
count lt (count 1) 16 end endmodule
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T Flip-flops
// T type flip-flop built from D flip-flop and
inverter module t_ff(q, clk, reset) output
q input clk, reset wire
d d_ff dff0(q, d, clk, reset) not
not0(d, q) endmodule
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Ripple Counter
/ This is an asynchronout ripple carry
counter. It is 4-bits wide. / module
ripple_carry_counter(q, clk, reset) output
30 q input clk, reset t_ff
tff0(q0, clk, reset) t_ff tff1(q1,
q0, reset) t_ff tff2(q2, q1, reset)
t_ff tff3(q3, q2, reset) endmodule
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Up/Down Counter
// 4-bit up/down counter module up_dwn(cnt, up,
clk, nclr) output 30 cnt input
up, clk, nclr reg 30 cnt always
_at_(posedge clk) begin if (nclr) cnt lt 0
else if (up) cnt lt cnt 1 else cnt
lt cnt - 1 end endmodule
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Shift Register
// 4 bit shift register define WID 3 module
serial_shift_reg(sout, pout, sin, clk)
output sout output WID0 pout
input sin, clk reg WID0 pout
always _at_(posedge clk) begin pout lt sin,
poutWID1 end assign sout
pout0 endmodule
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Universal Shift Register
// 4 bit universal shift register module
universal(pout, pin, sinr, sinl, s1, s0, clk)
output 30 pout input sinl, sinr,
clk, s1, s0 input 30 pin reg
30 pout always _at_(posedge clk) begin
case (s1,s0) 0 pout lt pout
1 pout lt pout20, sinl
2 pout lt sinr, pout31 3 pout
lt pin endcase end endmodule
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Mealy FSM
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DRAM Controller
// Example of a Mealy machine for a DRAM
controller module mealy(clk, cs, refresh, ras,
cas, ready) input clk, cs, refresh output
ras, cas, ready parameter s0 0, s1 1,
s2 2, s3 3, s4 4 reg 20
present_state, next_state reg ras, cas,
ready // state register process always _at_
(posedge clk) begin present_state lt
next_state end
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DRAM Controller (part 2)
// state transition process always _at_
(present_state or refresh or cs) begin case
(present_state) next_state s0 ras
1'bX cas 1'bX ready 1'bX
s0 begin if (refresh)
begin next_state s3
ras 1'b1 cas 1'b0
ready 1'b0 end
else if (cs) begin
next_state s1 ras 1'b0
cas 1'b1 ready 1'b0
end else
begin next_state s0
ras 1'b1 cas 1'b1
ready 1'b1
end end
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DRAM Controller (part 3)
s1 begin next_state s2
ras 1'b0 cas 1'b0 ready
1'b0 end s2 begin if
(cs) begin next_state
s0 ras 1'b1
cas 1'b1 ready 1'b1
end else begin
next_state s2 ras 1'b0
cas 1'b0 ready
1'b0 end end s3
begin next_state s4 ras
1'b1 cas 1'b0 ready 1'b0
end s4 begin next_state
s0 ras 1'b0 cas 1'b0
ready 1'b0 end
endcase end endmodule
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1-bit ALU Module
// 1-bit alu like the one in Mano text
(ECE580) module alui(aci, clk, control, acip1,
acim1, dri) output aci input clk input
20 control input acip1, acim1, dri reg
aci parameter nop 3'b000, com 3'b001,
shr 3'b010, shl 3'b011, dr 3'b100,
clr 3'b101, and_it 3'b110 always
_at_ (posedge clk) begin case (control)
nop aci lt aci
com aci lt aci shr aci
lt acip1 shl aci lt acim1
dr aci lt dri
clr aci lt 0 and_it aci
lt aci dri default aci lt
aci endcase end endmodule
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Modeling Memory
// memory model, bidir data bus module
memory(data, addr, ce, rw) inout 70
data input ce, rw input 50 addr
reg 70 mem063 reg 70
data_out tri 70 data wire
tri_en always _at_(ce or addr or rw or data)
begin if (ce) if (rw)
data_out memaddr else
memaddr data end assign tri_en
ce rw assign data tri_en ? data_out
8'bz endmodule
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Binary to BCD
// // We need to convert a 5-bit binary number //
to 2 BCD digits // module bin2bcd(bcd1, bcd0,
bin) output 30 bcd1 output
30 bcd0 input 40 bin reg
30 bcd1 reg 30 bcd0 reg
70 bcd integer i always _at_ (bin)
begin bcd1 4'd0 bcd0 4'd0
for (i0 i lt 5 i i 1) begin
if (bcd0 gt 4'd5) bcd0 bcd0 4'd3
if (bcd1 gt 4'd5) bcd1 bcd1 4'd3
bcd bcd1, bcd0 bcd bcd ltlt 1
bcd0 bin4-i bcd1
bcd74 bcd0 bcd30
end end endmodule