Digital Systems Design

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Digital Systems Design

• Shyue-Kung Lu
• Department of Electronic Engineering

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Syllabus

• Recommended Texts
• 1. Michael D. Ciletti, Advanced Digital
  Design with the Verilog HDL,
• Prentice Hall (????)
• References
• 1. Richard S. Sandige, Digital Design
  Essentials, Prentice Hall (????)
• 2. John F. Wakerly, Digital Design
  Principle and Practices, Prentice Hall
• (????)
• 3. M. Morris Mano, Digital Design, Prentice
  Hall, Third Edition (???
• ?,04-27088787)
• 4. M. Morris Mano, Digital Logic and
  Computer Design Fundamentals,
• Prentice Hall (????)
• Grades 1. ?? 25 2. ??? 30 3. ??? 30 4.
  Project 15
• Project ??? FPGA ??????

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Digital Systems Design

• Course Overview
• Review of combinational and sequential logic
  design
• Introduction to synthesis with HDLs (Verilog
  HDL)
• Programmable logic devices (CPLD and FPGA)
• State machines, datapath controllers, RISC CPU
• Architectures and algorithms for computation
• Synchronization across clock domains
• Static Timing Analysis
• Fault simulation and testing, JTAG, BIST

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Chapter 1-3Review of Digital Systems
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Logic Level Ranges of Voltage for a Digital
Circuit
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Representations of a Digital Design
Z A' B' (C D) (A' (B' (C D)))
Logic expression
True table
Transistor circuit
Gate netlist
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Basic Primitives
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Some Common IC Gates
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Typical IC Datasheet
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Combinational Logic Circuit

• Combinational circuit logic circuit whose
  outputs at any time are determined directly and
  only from the present input combination.
• A combinational circuit performs a specific
  information-processing operation fully specified
  logically by a set of Boolean functions.
• Sequential circuit one that employ memory
  elements in addition to (combinational) logic
  gatestheir outputs are determined from the
  present input combination as well as the state of
  the memory cells.

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Block Diagram of a Combinational Circuit
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Combinational Modules

• Ripple Carry Adder
• Carry Look ahead Adder
• Binary Adder-Subtractor
• BCD Adder
• Magnitude Comparator
• Binary Multiplier
• Decoder/Encoder
• Priority Encoder
• Multiplexers/Demultiplexers
• Three-State Gates

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Sequential Circuits
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Synchronous Clocked Sequential Circuit
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Clock Response in Latch and Flip-Flop
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Setup time and Hold Time
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DFF
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JKFF
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JKFF
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Characteristic Tables and Equations
D Q(t1)
0 1 0 1 Reset Set
J K Q(t1)
0 0 0 1 1 0 1 1 Q(t) 0 1 Q(t) No change Reset Set Complement
T Q(t1)
0 1 Q(t) Q(t) No change Complement

• Q(t 1) D (D Flip-Flop)
• Q(t 1) JQ KQ (JK Flip-Flop)
• Q(t 1) TQ TQ (T Flip-Flop)

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DA A ? x ? y
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Mealy Machine
Outputs dependent on inputs and state
variables. Are inputs synchronized with clock?
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Moore Machine
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4-Bit Register

• A register is a group of flip-flops, read/written
  as a unit.
• A register that goes through a prescribed
  sequence of states upon the application of input
  pulses is called a counter.

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Register withParallel Load
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Shift Register
1
1
0
0
1
1
0
1
0
Edge trigger or level trigger?
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Synchronous Counter

• No need to go through a sequential logic design
  process.
• The flip-flop in the least significant position
  is complemented with every pulse. A flip-flop in
  any other position is complemented when all the
  bits in the lower significant positions are equal
  to 1.