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Using Hierarchy in Design Automation:

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Title: Hierarchical Fault Collapsing for Logic Circuits Author: sandira Last modified by: agrawvd Created Date: 9/3/2004 5:18:11 PM Document presentation format – PowerPoint PPT presentation

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Title: Using Hierarchy in Design Automation:


1
  • Using Hierarchy in Design Automation
  • The Fault Collapsing Problem

Raja K. K. R. Sandireddy Intel
Corporation Hillsboro, OR 97124,
USA raja.sandireddy_at_intel.com
Vishwani D. Agrawal Auburn University Auburn, AL
36849, USA vagrawal_at_eng.auburn.edu
11th VLSI Design and Test Symposium Kolkata,
August 8-11, 2007
2
Outline
  • Introduction
  • Main idea
  • Background on fault collapsing
  • Hierarchical fault collapsing
  • Method
  • Advantages
  • Smaller collapse ratio
  • Reduced CPU time
  • Results
  • Conclusion

3
The General Idea of Hierarchy
Lowest-level block (gates and interconnects), anal
yzed in detail, saved in library.
Circuit (top level In hierarchy)
Subnetwork analyzed once, placed in library.
interconnects
Analysis at nth level 1. Copy preprocessed
internal detail of n-1 level from
library. 2. Process nth level interconnects.
4
Background on Fault Collapsing
Test Vector Generation Flow
  • DUT
  • Generate fault list
  • Collapse fault list
  • Generate test vectors

Fault model
Required fault coverage
5
Structural Fault Collapsing
Total faults 6
  • Equivalence Collapsing It is the process of
    selecting one fault from each equivalence fault
    set.
  • Equivalence collapsed set a0, b0, c0, c1
  • Collapse ratio 4/6 0.67
  • Dominance Collapsing From the equivalence
    collapsed set, all dominating faults are left out
    retaining their respective dominated faults.
  • Dominance collapsed set a0, b0, c1
  • Collapse ratio 3/6 0.5

6
An Example of Structural Collapsing
a0 a1
a
c0 c1
f0 f1
e0 e1
b0 b1
b
c
e
f
d0 d1
d
Total faults 12 Structural Equivalence
collapsed faults 8 Structural Dominance
collapsed faults 6 Three tests, 00,01,10,
cover all faults
7
Functional Collapsing
  • Two faults are functionally equivalent if the
    corresponding faulty functions are identical.
  • Functional dominance can be similarly defined.
  • Determination of functional equivalence or
    dominance is as complex as test generation or
    equivalence checking.
  • A graph-theoretic method for fault collapsing
  • A. V. S. S. Prasad, V. D. Agrawal and M. V. Atre,
    A New Algorithm for Global Fault Collapsing into
    Equivalence and Dominance Sets, Proc. Int. Test
    Conf., 2002, pp. 391-397.
  • V. D. Agrawal, A. V. S. S. Prasad and M. V. Atre,
    Fault Collapsing via Functional Dominance,
    Proc. Int. Test Conf., 2003, pp. 274-280.

8
Dominance Collapsed Set
a0 a1
a
c0 c1
f0 f1
b0 b1
e0 e1
b
c
e
f
d0 d1
d
Total faults 12 Structural Equivalence
collapsed faults 8 Structural Dominance
collapsed faults 6 Functional dominance
collapsed faults 4 Two tests, 01,10, cover
all faults
9
Functional Collapsing XOR Cell
Functional dominance examples d0 ? j0, k1 ? g0
c0 c1
All faults 24 Str. Equ. Faults 16 Str. Dom.
Faults 13 Func. Dom. Faults 4
c
d0 d1
h
j
a
g
m
d
e
b
k
i
f
10
Hierarchical Fault Collapsing
  • Create a library
  • For smaller (gate-level) circuits, exhaustive
    (functional) collapsing may be done.
  • For larger circuits, use structural collapsing.
  • For hierarchical circuits, at any level of
    hierarchy, say nth level
  • Read-in preprocessed (library) collapse data of
    (n-1) level sub-circuits.
  • Structurally collapse the interconnects and gate
    faults of nth level.
  • R. K. K. R. Sandireddy and V. D. Agrawal,
    Diagnostic and Detection Fault Collapsing for
    Multiple Output Circuits, Proc. Design,
    Automation and Test in Europe Conf., March 2005,
    pp. 10141019.
  • R. Hahn, R. Krieger, and B. Becker, A
    Hierarchical Approach to Fault Collapsing, Proc.
    European Design Test Conf., 1994, pp. 171176.

11
A Fault Collapsing Library
Cell name Cell characteristics Cell characteristics Cell characteristics Cell characteristics Collapsed fault set size Collapsed fault set size Collapsed fault set size Collapsed fault set size Func. coll. CPU (s)
Cell name No. of inputs No. of outputs No. of gates Total faults Structural Structural Functional Functional Func. coll. CPU (s)
Cell name No. of inputs No. of outputs No. of gates Total faults Equ Dom Equ Dom Func. coll. CPU (s)
Logic gates n 1 1 2n2 n2 n1 n2 n1 -
XOR 2 1 4 24 16 13 10 4 7.9
HA 2 2 5 30 20 16 15 6 9.1
FA 3 2 11 60 38 30 26 12 15.7
Sun Ultrasparc 5_10 (360MHz, 128MB)
12
Collapse Ratios for Ripple-Carry Adders
Collapse ratio
Total faults 234 1,858 14,850 118,786
475,138
In hierarchical collapsing, faults in lowest
level cells (XOR, full-adder, half-adder) are
functionally collapsed.
Programs used 1. Hitec (obtained from Univ. of
Illinois at Urbana-Champaign) 2. Fastest
(obtained from Univ. of Wisconsin at
Madison) 3. Our program (Auburn Univ.)
13
CPU Time (sec) Improvement by Hierarchy for
Ripple-Carry Adder
14
Rents rule
  • Rents Rule Number of inputs and outputs
    terminals (T) for a typical block containing G
    logic gates is given by
  • T K Ga
  • a 0.5 to 0.65
  • CPU time for collapsing a large hierarchical
    circuit is dominated by the time taken to build
    the structure of the circuit which is
    proportional to the T 2 (ref our previous work).

15
Hierarchical 8-Bit Ripple Carry Adder
Here a 1.0, hence the total collapse time is
quadratic in circuit size as observed in our
experiment.
16
Hierarchical Array Multiplier
n n multiplier
n/2n/2
n/2n/2
n/2n/2
Inputs
Outputs
prop. to vG
prop. to vG
Here a 0.5, hence we expect the total collapse
time to grow linearly with circuit size.
17
Collapse Ratios for Array Multipliers
Collapse ratio
Total faults 84 726 3762
16,842 71,034 291,546 1,181,082
In hierarchical collapsing, faults in lowest
level cells (XOR, full-adder, half-adder) are
functionally collapsed.
Programs used 1. Hitec (obtained from Univ. of
Illinois at Urbana-Champaign) 2. Fastest
(obtained from Univ. of Wisconsin at
Madison) 3. Our program (Auburn Univ.)
18
CPU Time Improvement by Hierarchy for Array
Multipliers
19
Conclusion
  • Benefits of hierarchical fault collapsing
  • Better (lower) collapse ratios due to functional
    collapsing of library cells.
  • Order of magnitude reduction in collapse time.
  • Possible benefits of smaller fault sets
  • Fewer test vectors
  • Efficient fault simulation
  • Easier fault diagnosis
  • Further investigations
  • Structural problems (testability measures, static
    timing analysis, physical design, etc.) may be
    solved using hierarchy.
  • Functional problems (ATPG, simulation, etc.) may
    require new hierarchical algorithms.

128-bit multiplier
Dom. Collapsed Set Size (Collapse Ratio) Dom. Collapsed Set Size (Collapse Ratio) CPU s CPU s
Flat Hierarchical Flat Hier
53,4284 (0.45) 26,5824 (0.23) 27645 40
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