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Sources of Component Failures

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Sources of Component Failures design errors soft errors permanent transient Demand integrated silicon debug and fault diagnosis solutions soft deterministic – PowerPoint PPT presentation

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Title: Sources of Component Failures


1
Sources of Component Failures
design errors
soft errors
permanent
transient
Demand integrated silicon debug and fault
diagnosis solutions
soft
deterministic
Failed Components
SEU - soft errors
probabilistic
hard
Design errors
random defects
parametric variations
parametric
catastrophic
Parametric variations
Random Defects
On-Die Temperature variations
2
Integrated Diagnosis for Design Manufacturing
  • Three different tasks but similar underlying
    principles
  • Design Error Diagnosis
  • Complementing either formal verification or
    simulation-based verification
  • Silicon Debug
  • Diagnosing design bugs using one or several
    fabricated devices
  • Fault Diagnosis
  • Based on a small number of failed chip data
  • Based on a large number of chip data

3
Reconfiguration
  • Situation 100M transistors, unlikely all of them
    within spec range and completely functional
  • Reconfiguration may be imperative
  • Self-test -gt diagnosis -gt reconfiguration
  • Done in several steps from wafer probe to field
  • Sounds familiar?
  • Memory self-test, self-diagnosis, self-repair,
    fault tolerance
  • RF adding digital circuitry for self-calibration
  • fine-tuning performance
  • more robust to process, temperature and voltage
    variations
  • yield improvement

4
Reliability Re-configurability
  • Topics
  • Integrated diagnosis for design and manufacturing
  • Embedded memory
  • Random logic
  • Regular ASIC
  • Reconfiguration for reliable design
  • Self-calibration architectural design
  • Timing-error-tolerant architectural design
  • DFM new computational and algorithmic aspects
    of OPC PSM for sub-45nm technologies
  • Team
  • US UCSB
  • Taiwan NTHU, NTU
  • China ZJU

5
Fundamental Algorithms
  • Hybrid Constraint Solver
  • Integrating Boolean SAT with Linear Integer
    Arithmetic Solving for Sequential Systems
  • For RTL system-level verification, test and
    synthesis applications

6
Education
  • Architecture and System issues for nano technology

7
Collaboration
  • Kevin Wang UCLA
  • Evelyn Hu UCSB
  • Andy Yao - TsingHua

8
Prof. Yan
  • DFM OPC and PSM for sub-50nm technology
  • Formal verification
  • Focus on computational and algorithmic aspects of
    nano-electronics
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