Use%20of%20Hierarchy%20in%20Fault%20Collapsing

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• Use of Hierarchy in Fault Collapsing

Vishwani D. Agrawal Auburn University Auburn, AL
36849, USA
Raja K. K. R. Sandireddy Intel
Corporation Hillsboro, OR 97124, USA
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Outline

• Introduction
• Main idea
• Background on fault collapsing
• Hierarchical fault collapsing
• Method
• Advantages
• Smaller collapse ratio
• Reduced CPU time
• Results
• Conclusions

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The General Idea of Hierarchy
Lowest-level block (gates and interconnects), anal
yzed in detail, saved in library.
Circuit (top level In hierarchy)
Subnetwork analyzed once, placed in library.
interconnects
Analysis at nth level 1. Copy preprocessed
internal detail of n-1 level from
library. 2. Process nth level interconnects.
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Background on Fault Collapsing
Test Vector Generation Flow

• DUT
• Generate fault list
• Collapse fault list
• Generate test vectors

Fault model
Required fault coverage
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Structural Fault Collapsing
Total faults 6

• Equivalence Collapsing It is the process of
  selecting one fault from each equivalence fault
  set.
• Equivalence collapsed set a0, b0, c0, c1
• Collapse ratio 4/6 0.67
• Dominance Collapsing From the equivalence
  collapsed set, all dominating faults are left out
  retaining their respective dominated faults.
• Dominance collapsed set a0, b0, c1
• Collapse ratio 3/6 0.5

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Functional Collapsing XOR Cell
Functional dominance examples d0 ? j0, k1 ? g0
c0 c1
All faults 24 Str. Equ. Faults 16 Str. Dom.
Faults 13 Func. Dom. Faults 4
c
d0 d1
h
j
a
g
m
d
e
b
k
i
f
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Hierarchical Fault Collapsing

• Create a library
• For smaller (gate-level) circuits, exhaustive
  (functional) collapsing may be done.
• For larger circuits, use structural collapsing.
• For hierarchical circuits, at any level of
  hierarchy, say nth level
• Read-in preprocessed (library) collapse data of
  (n-1) level sub-circuits.
• Structurally collapse the interconnects and gate
  faults of nth level.

• References
• R. K. K. R. Sandireddy and V. D. Agrawal,
  Diagnostic and Detection Fault Collapsing for
  Multiple Output Circuits, Proc. Design,
  Automation and Test in Europe Conf., March 2005,
  pp. 10141019.
• R. Hahn, R. Krieger, and B. Becker, A
  Hierarchical Approach to Fault Collapsing, Proc.
  European Design Test Conf., 1994, pp. 171176.

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Results Collapse Ratio Advantage
Collapse ratio
Total faults 60 3,714 59,394 1,116 2,646
In hierarchical collapsing, faults in lowest
level cells (XOR, full-adder) are functionally
collapsed.
Programs used 1. Hitec (obtained from Univ. of
Illinois at Urbana-Champaign) 2. Fastest
(obtained from Univ. of Wisconsin at
Madison) 3. Our program
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Fault Collapsing Time for Flattened Circuits
CPU time clocked on a 360MHz Sun UltraSparc 5_10
machine with 128MB memory.
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Analysis of CPU Time (s) for Flattened Circuits
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Analysis of CPU Time (s) for Hierarchical Circuits
Total
Library
Equiv.Dom.Collapsing
Structure Processing
0.10
0.07
0.01
0.01
64-bit
0.19
0.13
0.02
0.03
128-bit
0.39
0.19
0.02
0.05
256-bit
0.81
0.36
0.04
0.17
512-bit
1.82
0.73
0.08
0.55
1024-bit
4.72
1.52
0.20
2.10
2048-bit
14.3
3.1
0.37
9.25
4096-bit
50.2
6.0
0.79
40.1
8192-bit
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Comparison of CPU Times for Hierarchical and
Flattened Circuits
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CPU Time (s) Improvement by Hierarchy
Hierarchical circuit
Flattened circuit
Multi-level
Two-level
Our Program
Hitec
0.10
0.16
0.24
0.57
64-bit
0.24
0.32
0.75
1.47
128-bit
0.49
0.69
2.49
5.09
256-bit
1.05
1.52
9.38
19.5
512-bit
2.31
3.60
39.9
77.7
1024-bit
4.80
10.3
166.4
326
2048-bit
16.6
35.1
674.1
1258
4096-bit
55.0
127.2
2676
--
8192-bit
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CPU time (s) for Hierarchical Collapsing
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Rents rule

• Rents Rule Number of inputs and outputs
  terminals (T) for a typical block containing G
  logic gates is given by
• T K G
• 0.5 to 0.65
• For ripple carry adders, 1. CPU time for
  collapsing is proportional to G2.

G is proportional to area
a
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Hierarchical Multipliers
n n multiplier
n/2n/2
n/2n/2
n/2n/2
vG outputs
vG inputs
Here 0.5, hence we expect the total
collapse time to grow linearly with circuit size.
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Conclusions

• For larger circuits described hierarchically, use
  hierarchical fault collapsing.
• Hierarchical fault collapsing
• Better (lower) collapse ratios due to functional
  collapsed library
• Order of magnitude reduction in collapse time.
• Smaller fault sets
• Fewer test vectors
• Reduced fault simulation effort
• Easier fault diagnosis.

8192-bit Adder
Dom. Collapsed Set Size (Collapse Ratio) Dom. Collapsed Set Size (Collapse Ratio) CPU s CPU s
Flat Hierarchical Flat Hier.
229378 (0.48) 98304 (0.21) 2676 55
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• THANK YOU