Speed/Area Optimized 8-bit Adder Design

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Speed/Area Optimized 8-bit Adder Design
Delay(ms)Area(mm2) your number

• Name 1
• Name 2

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Design Summary

• Adder topology, Circuit Style(e.g. CSA, static
  CMOS)
• WHY about A, about D, other(e.g. moderate A,
  fast, regular design)
• Corner TT, temp25C
• If your design is dynamic, include clock tree
  power!
• Measure power over 20ns using test vectors from
  pg.5

(report the numbers with 3 decimal places)
(SCH) tp (ns) A (mm2)
(LAY) tp (ns) Aspect ratio
gates on crit path LAY tpA (msmm2)
(LAY) P (100MHz) Passed LVS Yes No
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Critical Path Analysis

• Input transition for critical path
• Highlight critical path
• block diagram of design
• indicate critical transition
• write down critical path equation

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Sizing Optimization

• illustration of gate level critical path
• MOS transistor detail of critical gates
• sizing numbers of the critical gates

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Functionality Check

• Input vectors (MSB-to-LSB)
• A 00000000 ? 10110110 ? 00101001
• B 00000000 ? 01011011 ? 01010110
• Cin 0 ? 1 ? 1
• plot S0-S7 Cout on three graphs (each bit has
  its own plot) for the above transition vectors
• Format see table(table should span whole page)
• X-axis 20ns range
• Last 5ns of the first vector
• Full 10ns for the second
• First 5ns of the last vector

S0 S3 S6
S1 S4 S7
S2 S5 Cout
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Layout Techniques

• show layout floorplan (indicate the location of
  main adder building blocks)
• use Cadence ruler to clearly indicate size in mm
• highlight critical path in your layout
• aspect ratio has to be lt 1.5
• pins must be on the top-level cell boundary
• label the pins in your layout