Speed/Area Optimized 8-bit Adder Design

1
Speed/Area Optimized 8-bit Adder Design
Delay(ms)Area(mm2) 1.72

• Albert H Chang
• Rustom Dessai

2
Design Summary

• Adder Topology Dynamic with Carry Bypass
• Manchester Carry Chain to generate Carries
• Use one transistor (as MUX) to bypass carry
• Transmission Gate to implement XOR
• Skew our Inverters to move Vm closer to Vdd
• WHY Small Area, Fast Circuit. Carry Select could
  be faster, but it would cause huge area penalty.
• Power from Clock 36.50uW

(SCH) tp (ns) 1.163 A (mm2) 1634.486
(LAY) tp (ns) 1.057 Aspect ratio 1.495
gates on crit path 5 LAY tpA (msmm2) 1.72
(LAY) P (100MHz) 4.396m Passed LVS Yes No
3
Critical Path Analysis
2 Bits
2 Bits
1 Bit
3 Bits
Bit 0-1
Bit 7
tsetup
tmux
tmux
tmux
Setup
Carry propagation
Setup
tsetup
Tadder2Tcarry2TmuxTsum
ONE transistor as MUX

• Input transition for critical path
• A 00000000 ?01010101
• B 00000000 ?10101010
• Ci0?1

NEED to propagate 0 carry through our
Manchester chain Pulling all our nodes down!
4
Sizing Optimization
Stage Z LE1 B1
16X
3
5
Functionality Check
Sum3
Sum6
Sum0
0
0
0
0
0
0
0
0
0
Sum4
Sum1
Sum7
1
0
0
0
0
1
0
0
1
Sum5
Sum2
Cout
0
0
0
0
0
0
1
0
0
6
Layout Techniques
Critical Path