MOUSETRAP%20Ultra-High-Speed%20Transition-Signaling%20Asynchronous%20Pipelines

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MOUSETRAPUltra-High-Speed Transition-Signaling
Asynchronous Pipelines

• Montek Singh Steven M. Nowick
• Department of Computer Science
• Columbia University, New York, NY 10027
• 2001 IEEE

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Agenda

• Review
• Introduction
• MOUSETRAP
• Preliminary Experiment Results
• Conclusions

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Review

• Synchronous pipeline
• Wave pipeline
• Clock-delayed domino
• Skew-tolerant domino
• Self-resetting circuits
• Asynchronous pipeline
• Micropipeline
• GasP
• IPCMOS

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Asynchronous circuits benefits

• No clock skew problem
• Low power consumption
• Faster speed (average case)
• Reduce global timing issues
• Avoid variations in fabrication,temperature,etc.
• Low EMI Noise

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Low Power Consumption

• On high-performance chips
• Clock power consumption is a significant
  proportion of total power consumption.
• Gated clocks reduce the wastage
• Make clock skew worse
• Incur some power cost
• All parts of the clocked circuits run the same
  frequency

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Performance

• Synchronous design must be toleranced for worst
  case conditions
• Fabrication, temperature, voltage, data values,
  Clock skew
• Asynchronous circuits self-adjust to the
  operating and data conditions

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Agenda

• Review
• Introduction
• MOUSETRAP
• Preliminary Experiment Results
• Conclusions

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Introduction

• Asynchronous Design Styles
• Protocol
• Level signaling (four phase)
• Transition signaling (two phase)
• Logic
• Bundled-data (ex signal-rail)
• Self-timed (ex dual-rail)

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Level signaling (four phase)

• A send data to B (active)
• Step 1A?put data in bus, set req 1
• Step 2B?get data from bus, set ack 1
• (return-to-zero phase)
• Step 3A?set req 0
• Step 4B?set ack 0

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Transition signaling (two phase)

• A send data to B (active)
• Step 1A?put data in bus, set req 1
• Step 2B?get data from bus, set ack 1
• Step 3A? put data in bus , set req 0
• Step 4B? get data from bus, set ack 0

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Introduction

• Asynchronous Design Styles
• Protocol
• Level signaling (four phase)
• Transition signaling (two phase)
• Logic
• Bundled-data (ex signal-rail)
• Self-timed (ex dual-rail)

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C-element

• ZnextABZ(AB)
• When A1,B1 ? Znext1
• When A0,B0 ? Znext0

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Micropipeline

• 4-phase latch FIFO

ack
req
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Bundled-data
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Self-timed

• Generate Completion-Detection signal
• Delay-Insensitive (DI) Coding
• exdual-rail coding (two phase coding)
• 00 -gt invalid value
• 01 -gt 0
• 10 -gt 1
• 11 -gt no use

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Self-timed (dual-rail coding)
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Performance Comparison of Asynchronous Adders
Mark A. Franklin Tienyo Pan
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Agenda

• Review
• Introduction
• MOUSETRAP
• Preliminary Experiment Results
• Conclusions

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Mousetrap

• Minimal-Overhead Ultrahigh-SpEed
  Transition-signaling Asynchronous Pipeline

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MOUSETRAP-FIFO
Latch delay is 110 ps XNOR delay is 65 ps
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MOUSETRAPwith logic (bundled data)
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Bundled data

• Bundled data scheme
• Reqn must arrive at stage N after the data
  inputs to that stage have stabilized.
• Worst-case delay
• Allow circuits to have hazards

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Delay Buffer

• Inverter chain
• A chain of transmission gates
• Duplicate the worst-case critical path
• More accurate delay
• More area-expensive

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Timing-forward latency
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Timing-Cycle time
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Standard synchronous pipeline

• Forward latency
• Cycle time

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MOUSETRAP-Setup time
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MOUSETRAP-Hold time
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Clocked-CMOS (C2MOS) logic
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C2MOSs benefits

• Smaller delay
• Smaller area
• Lower power consumption

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MOUSETRAP- C2MOS

• Forward latency
• Cycle time

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Handling wide datapaths

• Datapath partitioning
• Control kiting (buffer insertion)

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Optimization

• Sliding door
• Change MOSs width (lower )

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Non-Linear Pipeline-fork
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Non-Linear Pipeline-join
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experiment

• 0.25µm TSMC
• 2.5v , 300k
• A pass-gate implementation of an XNOR/XOR
• A standard 6 transistor pass-gate dynamic D-latch
• 0.6µm HP
• 3.3v ,300K
• A pass-gate implementation of an XNOR/XOR
• Clocked-CMOS style latch
• 10 stage, 16-bit datapath
• pre-layout simulation (HSPICE)

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result
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Conclusions

• Use small fast latches
• Low Latch controller overhead(XNOR)
• Transition-signaling protocol(efficient
  concurrent)
• Without complex timing design effort
• Variable-speed environment(elasticity)

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comparison

• IPCMOS (asynchronous interlocked pipelined CMOS)
• 3.34.5GHz
• IBM 0.18µm
• Post-layout simulation