Sequential Logic III

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Sequential Logic III

• Instructor Koling Chang

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Outline

• General Design Process for Sequential Circuit
• Finite State Machine (FSM)
• Synchronous vs. Asynchronous
• Hazards

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General Design Process

• FSM can be used to express the behavior of a
  sequential circuit
• Counters are a special case
• State transitions are indicated by arrows with
  labels X/Y
• X inputs that cause system state change
• Y output generated while moving to the next
  state
• Look at two examples
• Even-parity checker
• Pattern recognition

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General Design Process (cont.)

• Even-parity checker
• FSM needs to remember one of two facts
• Number of 1s is odd or even
• Need only two states
• 0 input does not change the state
• 1 input changes state
• Simple example
• Complete the design as an exercise

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Even Parity State Machine
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Even Parity FSM Truth Table
J X K X Y AX AX X ? A
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General Design Process (cont.)

• Pattern recognition example
• Outputs 1 whenever the input bit sequence has
  exactly two 0s in the last three input bits
• FSM requires three special states during the
  initial phase
• S0 - S2
• After that we need four states
• S3 last two bits are 11
• S4 last two bits are 01
• S5 last two bits are 10
• S6 last two bits are 00

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General Design Process (cont.)

• State diagram for the pattern recognition example

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General Design Process (cont.)

• Steps in the design process
• Derive FSM
• State assignment
• Assign flip-flop states to the FSM states
• Necessary to get an efficient design
• Design table derivation
• Derive a design table corresponding to the
  assignment in the last step
• Logical expression derivation
• Use K-maps as in our previous examples
• Implementation

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General Design Process (cont.)

• State assignment
• Three heuristics
• Assign adjacent states for
• states that have the same next state
• states that are the next states of the same state
• States that have the same output for a given
  input
• For our example
• Heuristic 1 groupings (S1, S3, S5)2 (S2, S4,
  S6)2
• Heuristic 2 groupings (S1, S2) (S3, S4)3 (S5,
  S6)3
• Heuristic 1 groupings (S4, S5)

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General Design Process (cont.)

• State table for the pattern recognition example

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General Design Process (cont.)
State assignment

• K-map for state assignment

K-map for state assignment
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General Design Process (cont.)

• Design table

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General Design Process (cont.)
K-maps for JK inputs
K-map for the output
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General Design Process (cont.)
Final implementation

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Synchronous vs. Asynchronous

• Combinational circuit may have hazards
• output circuit
• feedback circuit
• Due to propagation delays

x1
x2
fx1x2x2y
y
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Hazard in Combinational Circuit
x1
x2
fx1x2x2y
y
x1 1 y 1 x2 1 0 f 1
1
f
0
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Async. Sequential Circuit Example

• Is this a stable sequential circuit?

x1
x2
fx1x2x2f
y
X1X2 00 01 11 10
0
0
1
0
Y 0 1
1
1
1
0
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Synchronous Circuit

• Synchronous circuit is not sensitive to hazards

x1
x2
fx1x2x2f
y
D-ff
X1X2 00 01 11 10
0
0
1
0
Y 0 1
1
1
1
0
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Asynchronous Circuit

• Asynchronous circuit is used
• working with asynchronous inputs
• clock skews
• fast circuit without clock cycle constrains
• Dealing with hazards in asynchronous circuit is a
  specific topic.
• For synchronous circuit, never gate the clock!

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Never Gate the Clock

• When conditional latching is desired, use a
  loop-back with mux.

load condition
load condition
clk
clk
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Determine the Clock Rate Limit

• Maximum delay from a FF output to a FF input

B
A
D Q
D Q
C