DIGITAALITEKNIIKKA III 2006

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DIGITAALITEKNIIKKA III 2006

• Lesson 6/10
• 30.03.2006

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DT3-06 Time Table

1/5

2/5

3/5
) Arvosteltava laskuharjoitus

4/5

5/5
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Vastausharjoitustehtävään 1 sarjasta 2/5-06
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Vastausharjoitustehtävään 1 sarjasta
2/5-06jatkoa
Direct instantation
U1 entity work.FIR(FIR_63PIN_020306 port
map(data_in,C0,C1C2C3Y)

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VHDL Synthesis

• VHDL was originally designed as a hardware
  description language
• It was designed to model the behavior of existing
  hardware, not to specify the functionality of
  proposed hardware
• In 1987 when VHDL was originally written, there
  were no automatic synthesis tools in widespread
  use
• Parts of the VHDL are not suitable for synthesis

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High-level design flow
Specification
Architectural/algoritm design
Behavioural syhthesis
State machine/ RTL design
RTL syhthesis
Combinational logic design
Place and route
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RTL Synthesis

• The starting point of the synthesis process is a
  model, in VHDL, of the system we wish to build
• Three styles of VHDL
• Structural (components)
• Dataflow (signal assignments)
• Behavioral (process)

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IEEE standard 1076.6-1999

• defines a subset of VHDL for RTL synthesis
• purpose of it is to define the minimum subset
  that can be accepted by any synthesis tool

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Non-synthesizable VHDL

• AFTER, TRANSPORT, INERTIAL
• WAIT FOR
• FILE
• GENERIC
• ACCESS
• Initial values of signals and variables will be
  ignored (use instead asynchronous set and reset)

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Basic data types
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INTEGER, REAL

• INTEGER -(231-1) to (231-1)
• REAL -1.0E38 to 1.0E38

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BIT, BIT_VECTOR

• type bit is (0,1)
• type BIT_VECTOR is array (NATURAL range ltgt) of
  BIT
• type std_logic is
• (U, X, 0, 1, Z, W, L, H,-)
• type std_logic_vector is array
• (NATURAL range ltgt) of std_logic

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std_logic (resolved type)

• type std_logic is
• (U,-- Uninitialized
• X, -- Forcing Unknown
• 0, -- Forcing 0
• 1, -- Forcing 1
• Z, -- High Impedance
• W, -- Weak Unknown, (Weak 1)
• L, -- Weak 0, Logic 0 (read)
• H, -- Weak 1, Logic 1 (read)
• - -- Dont care
• )

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std_logic

• Nine std_logic values make it possible to
  accurately model the behaviour of a digital
  circuit during simulation
• For synthesis users std_logic has additional
  benefits ,
• for describing circuits that involve output
  enables (3-state)
• and
• for specifying dont-care logic that can be used
  to optimize the combinational logic requirements
  of a circuit
• The most important reason to use standard logic
  types is portability interfacing to other
  components

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Arithmetics in VHDL
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Arithmetic operators

• addition
• - subraction
• multiplication
• / division
• abs absolute value
• rem reminder
• mod modulus
• exponentiation
• Arithmetic operators are predefined for data
  types integer, real and time

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Arithmetic operators

• The majority of synthesis tools support , -
  and for integers. However they are not
  supported for data types real and time
• Advanced synthesis tools support , - ,
  and for std_logic_vector type data

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Example Addition in VHDL
Library ieee use ieee.std_logic_1164.ALL use
ieee.std_logic_unsigned.ALL -- needed for
with std_logic_vectors entity ex is port ( a,b
in std_logic_vector(2 downto 0) c,d in integer
range 0 to 15 q1 out std_logic_vector(2 downto
0) q2 out integer range 0 to
30) end architecture rtl of ex is begin q1 lt
a b q2 lt c d end
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Yhteenlaskun RTL-VHDL-synteesi
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Yhteenlaskun kriittinen polku
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Standardilogiikkavektorien syntesoituva
kertolasku VHDL-kielellä
library ieee use ieee.std_logic_1164.ALL use
ieee.std_logic_unsigned.ALL entity v_mult
is port ( a,b in std_logic_vector(3 downto
0) c out std_logic_vector(7 downto
0) ) end architecture rtl of V_mult
is begin c lt ab end
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Kertolaskun RTL-synteesi
Summain
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(No Transcript)
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Kertojan kriittinen polku
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Kertojan summainlohkon kriittinen polku
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Behavior of IFT (ATU-R Tx)
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Behavior of FT (ATU-C Rx)
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Inferred flip-flops and latches

• There are no reserved word in VHDL to specify
  whether a model is combinational or sequential
  and whether any sequential logic is synchronous
  or asynchronous
• One of the most likely error is the creation of
  additional flip-flops or latches

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Inferred flip-flops and latches

• A FF or latch is synthesized if a signal or
  variable holds its value over a period of time
• All signals and variables to which assignments
  are made in a process containing a WAIT
  statement must be held in registers
• If a CASE or IF statement is incomplete a FF or
  latch is created

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Flip-flop and latch

• The term flip-flop ( FF) refers to a memory
  element triggered by an edge of the clock
• Latch refers to a level-sensitive device,
  controlled by some signal other than the clock
• A FF would be created if the edge of a signal is
  used in a WAIT, IF or CASE statement
• A latch would be created if the level value of a
  signal we used instead

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Level sensitive latch
p0process (Ctrl, A) is begin if (ctrl 1)
then Z lt A end if end process p0
p0process (Ctrl, A) is begin if (ctrl 1)
then Z lt A else Z lt 0
end if end process p0
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Level sensitive latch
p0process (Sel, A, B) is begin case Sel is
when 00 gt Y lt A when 01 gt Y lt B
when others gt null end case end process
p0
Y lt D when E 1 else Y
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Edge-sensitive flip-flop
p0process is begin wait untill (clock
1) Q lt D end process p0
RTL synhesizable process should have exactly one
WAIT UNTIL statement. This WAIT UNTILstatement
must be the first executable line of the process
and must depend only one transition of one
signal
p0process (clock) is begin if
rising_edge(Clock) then Q lt D end
if end process p0
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Edge-sensitive flip-flop
p0process (clock, reset) is begin if (reset
0) then Q lt 0 elsif
rising_edge(clock) then Q lt D end
if end process p0
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Variable in edge-sensitive process
p0process (clock) is begin if
rising_edge(Clock) then P lt A and B z
lt P or C end if end process p0
p0process (clock) is variable P
std_logic begin if rising_edge(Clock) then
P A and B z lt P or C end if end
process p0
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Reuna-aktiivisuus VHDL-koodissa (monisteen
sivuilla 103 105)
- attribuutti last_value
- kello CLK on tyyppiä bit

• rising_edge funktio on
• std_logic_1164-paketissa

- wait until prosessin sisällä
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Tähän 30.3.2006