Topic 11b: Asynchronous Logic Design III

1
Topic 11bAsynchronous Logic Design III

• \SFSU ENGR 852
• Spring 2003
• 4/28

2
This Lecture

• The Final Steps of Asynchronous Circuit Design
• Asynchronous Examples

3
Asynchronous FSM Design Steps

• Construct a primitive flow table from the word
  statement of the problem
• Derive a minimum-row primitive flow table or
  reduced primitive flow table by eliminating
  redundant, stable total-states
• Convert the resulting table to Mealy form, if
  necessary, so that the output value is associated
  with the total state rather than the internal
  state
• Derive a minimum-row flow table, or merged flow
  table, by merging compatible rows of the reduced
  primitive flow table using a merger diagram.
  (Note The solution is not necessarily unique)
• Perform race-free, or critical race-free, state
  assignment, adding additional states if necessary
• Complete the output table to avoid momentary
  false outputs when switching between stable total
  states
• Draw logic diagram that shows ideal combinational
  next-state and output functions as well as
  necessary delay elements.

4
Design Example 1

• An asynchronous network has two inputs and one
  output.
• The input sequence X1X200, 01, 11 causes the
  output Z to become 1.
• The next input change then causes the output to
  return to 0.
• No other input sequence will produce a 1 output.

X1 X2
Z
5
Design Example 1Step 1 Primitive Flow Table

• Primitive flow table (The final lines)
• Primitive flow table Only one stable state per
  row is allowed. Every change in input must cause
  an internal state change as well as a total state
  change.
• State 5 6 cannot lead to a 1 output without
  there being a reset first.

X1X2
6
Class Question 2

• Derivation of Primitive Flow Table

Clk G
00 01 11 10 Z
State 1 1 3 - 2 0
State 2 1 - 2 0
State 3 3 4 - 0
State 4 - 3 4 1
State 5 1 - - 5 1
State 6 - 3 6 - 0
7
Class Question 3(Removal of Redundant States)

• Remove redundant states

8
Asynchronous FSM Design Steps

• Construct a primitive flow table from the word
  statement of the problem
• Derive a minimum-row primitive flow table or
  reduced primitive flow table by eliminating
  redundant, stable total-states
• Convert the resulting table to Mealy form, if
  necessary, so that the output value is associated
  with the total state rather than the internal
  state
• Derive a minimum-row flow table, or merged flow
  table, by merging compatible rows of the reduced
  primitive flow table using a merger diagram.
  (Note The solution is not necessarily unique)
• Perform race-free, or critical race-free, state
  assignment, adding additional states if necessary
• Complete the output table to avoid momentary
  false outputs when switching between stable total
  states
• Draw logic diagram that shows ideal combinational
  next-state and output functions as well as
  necessary delay elements.

9
Design Example 1Step 3 Convert to Mealy

• Expand Output Columns

Inputs
Ouput Z
10
Design Example 1Step 4 Merger Diagram

• Draw a Line From States that can be Written as a
  Single Row
• States in Each Column are the Same
• Outputs Dont Conflict

2
1
11
Design Example 1 Step 4 Merger Diagram
2
Inputs
Ouput Z
1
3
6
5
4
12
Design Example 1 Step 4 Merger Diagram
2
Inputs
Ouput Z
1
3
6
5
4
Circle Groups Where Every Member has a Line to
Every Other Member
13
Design Example 1 Step 4 Merger Diagram
2
1
3
6
5
4
Merge Largest Group First. Then Merge Next
Largest NONOVERLAPPING Group Next Until no More
States/Groups are Left.
14
Design Example 1 Step 4 Merger Diagram
2
1
3
6
5
4
Merge Largest Group First. Then Merge Next
Largest NONOVERLAPPING Group Next Until no More
States/Groups are Left.
15
Class Question 1

• Merge the Rows of this Table

Inputs
Clk G
00 01 11 10 Z
State 1 1 3 - 2 0
State 2 1 - 2 0
State 3 3 4 - 0
State 4 - 3 4 1
State 5 1 - - 5 1
State 6 - 3 6 - 0
16
Asynchronous FSM Design Steps

• Construct a primitive flow table from the word
  statement of the problem
• Derive a minimum-row primitive flow table or
  reduced primitive flow table by eliminating
  redundant, stable total-states
• Convert the resulting table to Mealy form, if
  necessary, so that the output value is associated
  with the total state rather than the internal
  state
• Derive a minimum-row flow table, or merged flow
  table, by merging compatible rows of the reduced
  primitive flow table using a merger diagram.
  (Note The solution is not necessarily unique)
• Perform race-free, or critical race-free, state
  assignment, adding additional states if necessary
• Complete the output table to avoid momentary
  false outputs when switching between stable total
  states
• Draw logic diagram that shows ideal combinational
  next-state and output functions as well as
  necessary delay elements.

17
Races

• In a feedback sequential circuit, a race is
  said to occur when multiple internal variables
  change state as a result of a single input
  variable changing state
• If the final state depends on the order in which
  the variables change, the race is said to be
  critical.

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Race Free State Assignment

• Race-free Means that Only ONE State Value can
  Change at a Time. If a You are in State 00 and
  Want to go to State 11, You Must Follow a Path
  Such as 00?01?11 OR 00?10 ?11

19
Design Example 1 Step 5 Critical Race-free
State Assignment

• Rename States

Inputs
Ouput Z
Inputs
Ouput Z
20
Design Example 1 Step 5 Critical Race-free
State Assignment

• With a Single-Bit Input Change How Can the State
  Change?

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Design Example 1 Step 5 Critical Race-free
State Assignment

• Possible State Assignments (What We Called State
  ID When We Did Sequential Circuit Design)
• Race-free Means That Only One Bit Changes Between
  States But There is no Assignment That Will
  Allow This.

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Design Example 1 Step 5 Critical Race-free
State Assignment

• Solution Add a State

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Design Example 1 Step 5 Critical Race-free
State Assignment

• Table Derivation
• Add State
• Add c?(d) ?b Transition Path

24
Design Example 1 Step 6 Complete Output Table
to Remove Glitches

• Table Derivation
• Fill in Outputs Corresponding to Unstable States
  to Avoid Momentary False Outputs During
  Transition

Inputs
Ouput Z
25
Shared Row Assignment Example Step 5 Critical
Race-free State Assignment

• Tool to Help With State Assignment Shared Row
  Assignment
• Random Example
• Required Transitions
• Col 00 E ? A D? B
• Col 01 A? B C, F ? D
• Col 11 B, F? C D? E
• Col 10 A, C?D E ? F

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Shared Row Assignment Example Step 5 Critical
Race-free State Assignment

• Consider Required Transition Col 00 E, C ? A
  D? B
• Could Implement as E?A, C?A OR E?C?A OR C?E?A
  OR Any One of Many Other Combinations
• To Avoid Critical Races, A C E State
  Assignments Must all Only Differ by One Bit.

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Shared Row Assignment Example Step 5 Critical
Race-free State Assignment

• K-maps Again
• As Many of The Connected States as Possible
  Should be Next to Each Other in a K-map.

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Shared Row Assignment Example Class Problem

• For the State Assignments in the K-maps to the
  right, Complete the Table Below.

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Shared Row Assignment Example Class Problem
(Dont Peak!)

• Paths That Need to be Looked at
• A?D (000?101) ?000?010?011?111?101
• B?C (001?111) ?001?011?111
• F?D (110?101) ? 110 ? 111 ? 101

30
Asynchronous FSM Design Steps

• Construct a primitive flow table from the word
  statement of the problem
• Derive a minimum-row primitive flow table or
  reduced primitive flow table by eliminating
  redundant, stable total-states
• Convert the resulting table to Mealy form, if
  necessary, so that the output value is associated
  with the total state rather than the internal
  state
• Derive a minimum-row flow table, or merged flow
  table, by merging compatible rows of the reduced
  primitive flow table using a merger diagram.
  (Note The solution is not necessarily unique)
• Perform race-free, or critical race-free, state
  assignment, adding additional states if necessary
• Complete the output table to avoid momentary
  false outputs when switching between stable total
  states
• Draw logic diagram that shows ideal combinational
  next-state and output functions as well as
  necessary delay elements.

31
Design Example 1 Step 6 Complete Output Table
to Remove Glitches

• Output Derivation

Ouput Z
32
Design Example 1 Step 6 Complete Output Table
to Remove Glitches

• Table Derivation
• Fill in Outputs Corresponding to Unstable States
  to Avoid Momentary False Outputs During
  Transition

Inputs
Ouput Z
33
Asynchronous FSM Design Steps

• Construct a primitive flow table from the word
  statement of the problem
• Derive a minimum-row primitive flow table or
  reduced primitive flow table by eliminating
  redundant, stable total-states
• Convert the resulting table to Mealy form, if
  necessary, so that the output value is associated
  with the total state rather than the internal
  state
• Derive a minimum-row flow table, or merged flow
  table, by merging compatible rows of the reduced
  primitive flow table using a merger diagram.
  (Note The solution is not necessarily unique)
• Perform race-free, or critical race-free, state
  assignment, adding additional states if necessary
• Complete the output table to avoid momentary
  false outputs when switching between stable total
  states
• Draw logic diagram that shows ideal combinational
  next-state and output functions as well as
  necessary delay elements.

34
Design Example 1 Step 7 Derive Logic

• Logic Derivation
• Derivation of Combinational Logic Blocks for Next
  State and Output.
• Delay Placement

35
Design Example 1 Step 7 Derive Logic

• Model (I/O)

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Design Example 1 Step 7 Derive Output Logic
X1X2 PS1PS0 Z
0 0 0 0 0 0 0 0 1 0 0
0 1 0 X 0 0 1 1 X 0 1
0 0 0 0 1 0 1 0 0 1 1
0 1 0 1 1 1 0 1 0 0 0
0 1 0 0 1 0 1 0 1 0
1 1 0 1 1 X 1 1 0 0
X 1 1 0 1 0 1 1 1 0 1 1
1 1 1 X
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Design Example 1 Step 7 Derive Output Logic
X1X2 PS1PS0 Z
Z (Output)
0 0 0 0 0 0 0 0 1 0 0
0 1 0 X 0 0 1 1 X 0 1
0 0 0 0 1 0 1 0 0 1 1
0 1 0 1 1 1 0 1 0 0 0
0 1 0 0 1 0 1 0 1 0
1 1 0 1 1 X 1 1 0 0
X 1 1 0 1 0 1 1 1 0 1 1
1 1 1 X
X1X2
PS1 PS0
____ ZX1PS1
PS1PS0
38
Design Example 1 Step 7 Derive Next State Logic
PS1 PS0 X1 X2
X1X2 PS1PS0 NS1NS0
NS1
0 0 0 0 0 0 0 0 0 1
0 0 0 0 1 0 X X 0
0 1 1 X X 0 1 0 0
0 0 0 1 0 1 0 1 0 1
1 0 1 1 0 1 1 1 0
1 1 0 0 0 0 1 1 0 0
1 0 1 1 0 1 0 0
0 1 0 1 1 X X 1 1 0 0
1 0 1 1 0 1 0 1 1
1 1 0 1 0 1 1 1 1
X X
NS0
NS
PS
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Design Example 1 Step 7 Derive Next State Logic
X1X2 PS1PS0 NS1NS0
NS1
0 0 0 0 0 0 0 0 0 1
0 0 0 0 1 0 X X 0
0 1 1 X X 0 1 0 0
0 0 0 1 0 1 0 1 0 1
1 0 1 1 0 1 1 1 0
1 1 0 0 0 0 1 1 0 0
1 0 1 1 0 1 0 0
0 1 0 1 1 X X 1 1 0 0
1 0 1 1 0 1 0 1 1
1 1 0 1 0 1 1 1 1
X X
X1X2
PS1 PS0
___
___ NS1X1X2PS0 X2PS1PS0
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Design Example 1 Step 7 Derive Next State Logic
X1X2 PS1PS0 NS1NS0
NS0
0 0 0 0 0 0 0 0 0 1
0 0 0 0 1 0 X X 0
0 1 1 X X 0 1 0 0
0 0 0 1 0 1 0 1 0 1
1 0 1 1 0 1 1 1 0
1 1 0 0 0 0 1 1 0 0
1 0 1 1 0 1 0 0
0 1 0 1 1 X X 1 1 0 0
1 0 1 1 0 1 0 1 1
1 1 0 1 0 1 1 1 1
X X
X1X2
PS1 PS0
___
____ NS0X1X2PS0 X1PS1PS0
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Final Circuit
____ ZX1PS1
PS1PS0
___
___ NS1X1X2PS0 X2PS1PS0
___
____ NS0X1X2PS0 X1PS1PS0
NS1 NS0
PS1 PS0
X1 X2
Z
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Class QuestionFundamental Mode FB Delay

• What feedback delay is required on the last
  circuit?

43
Completion Signals

• How is the done signal generated?

44
Completion SignalsDelay Elements
Logic Block
Data
Delay Block
Done
At design time, determine worst case delay from
START signal until data is ready and build a
block that produces a pulse at completion.
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Completion SignalsRedundant Signal Encoding

• Create block such that it has two outputs. While
  circuit is not stable, output is 0,0. When result
  is found, output is 0, 1 or 1, 0.