Flip Flops

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(No Transcript)
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Objectives

• Given input logice levels, state the output of
  an RS NAND and RS NOR.
• Given a clock signal, determine the PGT and NGT.
• Define Edge Triggered and Level Triggered.
• Draw a Clocked F/F with and Edge Triggered
  clock input and a Level Triggered clock input.

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LOGIC CIRCUITS
Logic circuits are classified into two groups
Combinational logic circuits
Logic gates make decisions
Basic building blocks include
Sequential logic circuits
Flip Flops have memory
Basic building blocks include FLIP-FLOPS
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FLIP-FLOPS

• Memory device capable of storing one bit
• Memory means circuit remains in one state after
  condition that caused the state is removed.
• Two outputs designated Q and Q-Not that are
  always opposite or complimentary.
• When referring to the state of a flip flop,
  referring to the state of the Q output.

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FLIP-FLOPS
Symbol
SET

• To SET a flip flop means to make Q 1
• To RESET a flip flop means to make Q 0

RESET
Truth Table
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FLIP-FLOPS

• The flip flop is a bi-stable multivibrator it
  has two stable states.
• The RS flip flop can be implemented with
  transistors.

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R-S FLIP-FLOP
Symbols
Truth Table
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R-S FLIP-FLOP Active-Low
NAND LATCH
DEMORGANIZED NAND LATCH
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ACTIVE-LOW R-S FLIP-FLOP TIMING DIAGRAMS
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R-S FLIP-FLOP Active-High
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ACTIVE-HIGH R-S FLIP-FLOP TIMING DIAGRAMS
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TEST
Memory
1. Logic gates make decisions, flip flops have
____________________? 2. One flip flop can store
how many bits? 3. What are the two outputs of a
flip flop? 4. When referring to the state of a
flip flop, were referring to the state of which
output? 5. What does it mean to SET a flip
flop? 6. What does it mean to RESET a flip flop?
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Q
Q-NOT
Q
Q 1
Q 0
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TEST
What is the mode of operation of the R-S
flip-flop (set, reset or hold)? What is the
output at Q from the R-S flip-flop (active LOW
inputs)?
High
Set
High
Hold
Low
Reset
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CLOCKED R-S FLIP-FLOP
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Clock Digital signal in the form of a rectangular
or square wave
Astable multivibrator
A clocked flip flop changes state only when
permitted by the clock signal
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TRIGGERING OF FLIP-FLOPS

• Level-triggering is the transfer of data from
  input to output of a flip-flop anytime the clock
  pulse is proper voltage level.

• Edge-triggering is the transfer of data from
  input to output of a flip-flop on the rising edge
  (L-to-H) or falling edge (H-to-L) of the clock
  pulse. Edge triggering may be either
  positive-edge (L-to-H) or negative-edge (H-to-L).
  

NGT-Negative Going Transition
PGT-Positive Going Transition
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CLOCKED R-S FLIP-FLOP
Symbols
Truth Table
Mode of operation Inputs
Outputs Clk S R
Q Q Hold pulse 0 0 no
change Reset pulse 0 1
0 1 Set pulse 1 0 1
0 Prohibited 1
1 0 0 NOTE Active-High inputs
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TEST
What is the mode of operation of the clocked R-S
flip-flop (set, reset, hold)? What is the output
at Q from the clocked R-S flip-flop (active HIGH
inputs)?
High
Set
High
Hold
Low
Reset
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CLOCKED R-S FLIP-FLOP TIMING DIAGRAMS
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POSITIVE EDGE TRIGGERED R-S FLIP-FLOP
Symbols
Truth Table
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POSITIVE EDGE TRIGGERED R-S FLIP-FLOP TIMING
DIAGRAMS
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NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP
Symbols
EDGE DETECTOR
Truth Table
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NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP TIMING
DIAGRAMS
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TEST
1. Type of flip flop where the outputs of circuit
can change state anytime one or more input
changes?
ASYNCHRONOUS
2. Type of flip flop where the clock signal
controls when any output can change state?
SYNCHRONOUS
3. What do we call a digital signal in the form
of a repetitive pulse or square wave?
CLOCK
4. Which is easier to design and troubleshoot,
clocked or not clocked flip flops?
Clocked flip flops are easier to troubleshoot
because we can stop the clock and examine one set
of input and output conditions.