Flip Flops

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(No Transcript)
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Objectives

• Draw the symbol for the D-Latch and D Flip Flop.
• Given a D flip flop and input waveforms, draw the
  output waveform for Q.
• Given a J-K flip flop and input waveforms, draw
  the output waveform for Q.
• Define Asynchronous and Synchronous.
• Given a J-K flip flop, identify the synchronous
  and asynchronous inputs.

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FLIP-FLOP TYPES

• RS FLIP FLOP (Reset/Set) a.k.a. Set/Clear
• Most basic flip flop can be made by cross
  coupling NAND or NOR gates
• Activating Set and Reset is invalid

• D Flip Flop (Data or Delay)
• Has only a single data input and clock input
• Input transfers to output on clock pulse

• T Flip Flop (Toggle)
• Output toggles on each clock pulse
• Q output divides clock frequency in half

• J-K Flip Flop
• Universal, can make all other flip flops
• Has no prohibited states

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POSITIVE LEVEL TRIGGERED D FLIP-FLOP
Symbol
Truth Table
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POSITIVE LEVEL TRIGGERED D FLIP-FLOP TIMING
DIAGRAMS
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POSITIVE EDGE TRIGGERED D FLIP-FLOP TIMING
DIAGRAMS
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NEGATIVE EDGE TRIGGERED T FLIP-FLOP
Symbol

• Output toggles on each clock pulse
• Q output divides clock frequency in half
• Usually made with JK Flip Flop

Truth Table
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NEGATIVE EDGE TRIGGERED T FLIP-FLOP Timing
Diagrams
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J-K FLIP-FLOP

• UNIVERSAL Flip Flop can make all others from JK
  (T, D and RS)
• The J input acts like SET, K acts like RESET
• No illegal state, activating both inputs causes Q
  to TOGGLE

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J-K FLIP-FLOP
Symbol
Truth Table
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NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP Timing
Diagrams
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POSITIVE EDGE TRIGGERED J-K FLIP-FLOP Timing
Diagrams
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ASYNCHRONOUS OVERRIDES
Asynchronous Inputs a.k.a. Overide Inputs operate
independent of the control and clock inputs
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J-K FLIP-FLOP ASYNCHRONOUS OVERRIDES
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J-K FLIP-FLOP
Symbol
Truth Table
Mode of Operation Inputs
Outputs PS Clr
Clk J K Q Q Asynchronous
set 0 1 x x x
1 0 Asynchronous reset 1
0 x x x 0
1 Prohibited 0 0
x x x 1
1 ------------------------------------------------
------------------------- Hold
1 1 0 0 no
change Reset 1
1 0 1 0 1 Set
1 1 1 0
1 0 Toggle 1
1 1 1 opposite x
Irrelevant H-to-L transition of clock pulse
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J-K FLIP-FLOP ASYNCHRONOUS OVERRIDES Timing
Diagrams
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TEST
Data
Delay
1. The D in D flip flop stands for _________
or _________ . 2. With a D flip flop, Q follows
_____ when triggered by the clock. 3. The J
input on a J-K flip flop acts like what input on
an RS Latch? 4. The K input on a J-K flip flop
acts like what input on an RS Latch? 5. What
inputs on a J-K flip flop are the Asynchronous
inputs? 6. What inputs on a J-K flip flop are
the Synchronous inputs?
D
Set
Reset
Preset/Set
Clear/Reset
J K