Unit 11 Latches and Flip-Flops

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Unit 11 Latches and Flip-Flops

• Fundamentals of Logic Design
• By
• Roth and Kinney

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11.1 Introduction

• Sequential circuitshave the property that the
  output depends not only on the present input but
  also on the past sequence of inputs.
• Latch--a memory element that has no clock input.
• Flip-flopa memory device that changes its output
  in response to a clock input and not in response
  to a data input.

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11.1 (cont.)

• Feedbackthe output of one of the gates is
  connected back into the input of another gate in
  the circuit.
• Stable states or conditionssee figure 11-2.

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11.2 Set-Reset Latch

• Simple Latchfeedback is introduced into a simple
  NOR circuit.
• See figures 11-3(a,b) and 11-4(a,b)
• SR0a stable condition can exist with P1 and Q
  0.
• S1 R0 circuit state changes to Q 1.
• S0 R0circuit state remains as Q1.
• S0R 1circuit state can change to Q0
• Note that SR1 is not allowed.
• Note also that PQ.

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11.2

• Figure 11-5 illustrates the cross-coupled form.
• S is for SET and R is for RESET
• Q 1 for SET
• Q 0 for RESET

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11.2 (cont.)

• Concepts
• Present state
• Next State Q
• Present output
• Table 11-1S-R Latch Next State and Output
• Figure 11-8 Derivation of Next state for an S-R
  Latch

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11.2 (cont.)

• Using NANDS for an S-R Latch
• See Figure 11-10 (page 342)

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11.3 Gated Latches

• Gated Latches have an additional inputthe enable
  or gate input.
• See Figure 11-11.
• Gated D Latch is shown in Figure 11-14.

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11.4 Edge-Triggered D Flip-Flop

• See Figure 11-17
• Rising Edge Trigger (change occurs on rising edge
  of the clock.)
• Falling Edge Trigger
• Truth Table and Characteristic (state) Equation
• Timing (see Figure 11-18).
• Fig. 11-20 illustrates the set up (tsu) time and
  the hold time (th).

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11.5 S-R Flip-Flop

• The S-R FF is similar to a latch, except now
  there is a clock.
• The Master-Slave Implementation is shown in
  Figure 11-23 (p.349)

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11.6 J-K Flip-Flop

• An extended version of the S-R FF inputs
• J (corresponds to S)
• K (corresponds to R)
• Clock
• Figure 11-24 illustrates the J-K FF.

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11.7 T Flip-Flop

• Toggle FFoften used to build counters.
• T input (T0 means no toggle T1 means toggle.
• Clock input
• Figure 11-26, page 351
• Figure 11-27, page 352
• Figure 11-28, page 352, implementations.

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11.8 Flip-Flops with Additional Inputs

• Additional Inputs can be used to initialize FFs.
• Figure 11-29Clear and Preset.
• Figure 11-31illustrates enable.

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11.9 Asynchronous Sequential Circuits

• Asynchronous Sequential Circuitsstate can change
  when input changes.

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11.10 Summary

• Characteristic Equations
• Page 357
• S-R latch or FF
• Gated D latch
• D FF
• Page 358
• D-CE FF
• J-K FF
• T FF