Computer architecture

1
Slide Set 14 Computer architecture
2
A simple architecture

• 16-bit address and data sizes
• common address and data bus
• 2s complement integer fixed-point arithmetic
• components
• memory
• ALU (add, shift, complement, transfer)
• MAR (memory address register)
• MBR (memory buffer register)
• IR (instruction register)
• ACC (accumulator)
• PSR (processor status register with CNZVI flags)
• 3-register index file
• 3 special registers for constants 0, 1, -1
• PC (program counter)

3
Architectural evolution Year Machine Registers
Architecture 1949 EDSAC 1 accumulator 1953 IBM
701 1 accumulator 1963 CDC 6600 8 load-store
1964 IBM 360 16 register-memory 1965 PDP-8 1
accumulator 1970 PDP-11 8 register-memory 197
2 Intel 8008 1 accumulator 1974 Motorola
6800 2 accumulator 1977 DEC VAX 16 register-me
mory 1978 Intel 8086 1 extended
accumulator 1980 Motorola 68000 16 register-memo
ry 1985 Intel 80386 8 register-memory 1985 MIPS
32 load-store 1986 HP PA-RISC 32 load-store 1
987 SPARC 32 load-store 1992 PowerPC 32 load-
store 1992 DEC Alpha 32 load-store from
Computer Organization and Design by Patterson
and Hennessy
4
16 instructions

• LDA (load accumulator from memory)
• STA (store accumulator to memory)
• ADD (add memory to accumulator)
• TCA (2s complement accumulator)
• HLT (halt)
• BRU (unconditional branch)
• BIP (branch on positive accumulator)
• BIN (branch on negative accumulator)
• RWD (read accumulator from input device)
• WWD (write accumulator to output device)
• SHL (shift accumulator left)
• SHR (shift accumulator right, extend sign)
• LDX (load index from memory)
• STX (store index to memory)
• TIX (increment index and test, if zero branch
• TDX (decrement index and test, if nonzero branch

5
Instruction format
15 11 10 9 8 7
0
address (8)
op code (5)
index (2)
indirect bit (1)

• Bit 11 is always zero, leaving 4 bits for 16
  instructions
• 00 indicates no indexing
• indexing takes preference over indirect
  (preindexed indirect)
• must use indirect addressing or indexing to
  access memory beyond 255

6
Program to add n numbers ORG 0 start laying
code a memory location 0xinit BSC 8 block
storage constant 8, this is ndata BSC -4, 6, 8,
3, 1, -7, 2, 14 these are the data to
addresptr BSC R result pointerR BSS 1 block
storage, 1 word ORG 100 continue laying code at
location 100 start LDX xinit, 1 n to index
register 1 LDA 0 immediate operand, clear
accumulatorloop ADD data - 1, 1 indexed
add TDX loop, 1 decrement and test index to
loop if nonzero STA resptr indirect store to
R HLT END start indicate code end and initial
PC
7
Assembles to (hex) Location Content0000 00080
001 FFFC0002 0006 0003 00080004 0003 0005 0
0010006 FFF90007 00020008 000E0009 000A 00
0A ------ 0064 C1000065 106A0066 3100 0067
F1660068 2409 0069 0000006A 0000
xinit BSC 8 data BSC -4, 6, 8, 3, 1, -7, 2,
14resptr BSC R R BSS 1 start LDX xinit,
1 LDA 0loop ADD data - 1, 1 TDX loop,
1 STA resptr
8
Fetch-defer-execute cycle fetch PC ? MAR M
MAR ? MBR MBR ? IR PC 1 ? PC 00 IR7-0
? MAR (00 IR7-0) INDEX ? MAR defer M
MAR ? MBR MBR ? MAR executeHLT 0 ?
RUNLDA M MAR ? MBR MBR ? ACC STA ACC ?
MBR MBR ? M MAR ADD M MAR ? MBR ACC MBR
? ACC TCA ACC ? ACC ACC 1 ? ACC BRU MAR ? PC
use if no index or LDX, STX, TIX, TDX use if
index 01, 10, 11
MAR has address of effective operand
RUN is flip-flop in control unit 0 stops clock
9
Data path
PC
Bus 2
MAR
Index file
Bus 1
RAM
Bus 3
Switch bank
MBR
Zero
IR
Plus one
Minus one
ACC
ADDCOMPSHLSHRTRA1TRA2
B
A
PSR
ALU
10
Bus 1i 1
Bus 2 i
ALU Logic
Bus 1i - 1
Bus 1 i
ADD
COMP
SHR
SHL
TRA1
TRA2
Bus 3 i
CO i - 1, i gt 0 0, i 0
FA
CI
A
S
B
CO
CI i 1, i lt 15 PSRC, i 15
?
?
if i 0
if i 15 sign extend
11
Control Unit
Index
controlsignals e.g. TCA
16
IR
Clock
16
? ? ?
PSR
5
Run
State
Data
Start
12
all control signals ORed at point of
application e.g. BUS 3 to MBR may originate in
several places
BUS 3 to MBR signals from various places
BUS 3
BUS 2
MBR
multiplexers
MBR to BUS 2signals
? ? ?
? ? ?
13

• Fetch needs 4 clock cycles
• T1 PC ? BUS 1, TRA1, BUS 3 ? MAR, READ
• T2 PC ? BUS 1, 1 ? BUS 2, ADD, BUS 3 ? PC,
  (READ)
• T3 MBR ? BUS 2, TRA2, BUS 3 ? IR
• T4 Index ? BUS 2, IR7-0 ? BUS 1, ADD, BUS 3 ?
  MAR
• Assumptions
• each Ti terminates with rising clock edge
• memory read captures MAR at end of T1, stores
  to MBR at end of T2
• IR to BUS 1 zeros high-order bits of bus
• Index to BUS 2 loads correct index commanded by
  IR9-8 or zero if no index (IR9-8 00) or
  if RWD, WWD, SHL, SHR, LDX, STX, TIX, TDX

14
Defer also uses 4 cycles T1 READ T2 idle
(READ) T3 MBR ? BUS 2, TRA2, BUS 3 ? MAR T4
idle Execute also uses 4 cycles (e.g. LDA) T1
READ T2 idle (READ) T3 MBR ? BUS 2, TRA2, BUS
3 ? ACC T4 idle
15

• Other execute examples
• STA
• T1 ACC ? BUS 1, TRA1, BUS 3 ? MBR
• T2 WRITE
• T3 idle
• T4 idle
• ADD
• T1 READ
• T2 idle (READ)
• T3 ACC ? BUS 1, MBR ? BUS 2, ADD, BUS 3 ? ACC
• T4 idle

16

• TCA
• T1 ACC ? BUS 1, COMP, BUS 3 ? ACC
• T2 ACC ? BUS 1, 1 ? BUS 2, ADD, BUS 3 ? ACC
• T3 idle
• T4 idle
• BRU
• T1 MAR ? BUS 1, TRA1, BUS 3 ? PC
• T2 idle
• T3 idle
• T4 idle

17

• BIP
• T1 If PSRN and PSRZ MAR ? BUS 1, TRA1, BUS
  3 ? PC Else idle
• T2 idle
• T3 idle
• T4 idle
• BIN
• T1 If PSRN MAR ? BUS 1, TRA1, BUS 3 ? PC
  Else idle
• T2 idle
• T3 idle
• T4 idle

18

• RWD
• T1 DIL ? ACC
• WWD
• T1 ACC ? DOL
• SHL
• T1 ACC ? BUS 1, SHL, BUS 3 ? ACC
• SHR
• T1 ACC ? BUS 1, SHR, BUS 3 ? ACC
• LDX
• T1 READ
• T2 idle (READ)
• T3 MBR ? BUS2, TRA2, BUS 3 ? Index
• T4 idle

19

• STX
• T1 Index ? BUS 2, TRA2, BUS 3 ? MBR
• T2 WRITE
• TIX
• T1 Index ? BUS 2, 1 ? BUS 1, ADD, BUS 3 ? Index
• T2 If Index 0 MAR ? BUS 1, TRA1, BUS 3 ? PC
• TDX
• T1 Index ? BUS 2, -1 ? BUS 1, ADD, BUS 3 ? Index
• T2 If Index 0 MAR ? BUS 1, TRA1, BUS 3 ? PC

20
T4
T1
T2
T3
PRE S Q R Q CLR
PRE S Q R Q CLR
PRE S Q R Q CLR
PRE S Q R Q CLR
MasterClear
PRE S Q R Q CLR
StartSwitch
RUNflip-flop
Ring Counterfor clock phases
Reset
Clock
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Fetch(00)
Defer(01)
State machine
Execute(10)

• all transitions at end of T4
• compress execution into fetch for SHL, SHR, HLT
• partially compress for RWD and WWD
• remain in execute for RWD and WWD while devices
  respond
• need new flip-flops Data, Input, Output in
  control unit

22
Revised fetch sequence T1 PC ? BUS 1, TRA1,
BUS 3 ? MAR, READ T2 PC ? BUS 1, 1 ? BUS 2,
ADD, BUS 3 ? PC, (READ) T3 MBR ? BUS 2, TRA2,
BUS 3 ? IR T4 Case SHR ACC ? BUS 1,
SHR, BUS 3 ? ACC, 00 ? State SHL ACC ?
BUS 1, SHL, BUS 3 ? ACC, 00 ? State HLT
Reset, 00 ? State RWD 0 ? Data, 1 ?
Input, 10 ? State WWD 0 ? Data, 1 ?
Output, ACC ? DOL, 10 ? State Else
Index ? BUS 2, IR7-0 ? BUS 1, ADD, BUS
3 ? MAR If IR10 01 ?
State Else 10 ? State
23
Revised execute sequence add 00 ? State to
T4 for all instructions except RWD,WWD
e.g. ADD T1 READ T2 idle (READ) T3 ACC ?
BUS 1, MBR ? BUS 2, ADD, BUS 3 ? ACC T4 00 ?
State
24

• For I/O instructions change execute sequence
• RWD
• T1 idle
• T2 idle
• T3 idle
• T4 If Data DIL ? ACC, 0 ? Input, 00 ? State
• WWD
• T1 idle
• T2 idle
• T3 idle
• T4 If Data 0 ? Output, 00 ? State

25
Fetch(00)
t2
t1
Defer(01)
t1 t2
always
t3
t1 SHL SHR HLT t2 IR10 t3 Data (RWD
WWD) With D flip-flops D1 Defer Execute
t3 Fetch t1 t2 D2 Fetch t2
Execute(10)
t3
26
SHLSHRHLT
t1
State machine implementation
t2
IR10
RWDWWD
t3
Data
t1
t2
t3
Fetch
Defer
Execute
Q1
D1
D Q Q
24 decoder
00
Q0
11
D2
D Q Q
T4
27
Hardwired Controller vs. Microprogrammed
Controller Hardware Fetch Logic
Fetch
PC ? BUS 1
TRA1
T1
BUS 3 ? MAR
READ
PC ? BUS 1
1 ? BUS 2
T2
ADD
BUS 3 ? PC
READ
MBR ? BUS 2
TRA2
T3
BUS 3 ? IR
28
Fetch
T4
Reset
HLT
IR15
Index ? BUS 2
IR7-0 ? BUS 1
TCA
ADD
BUS 3 ? MAR
LDX
SDX
IR7-0 ? BUS 1
TIX
TRA1
BUS 3 ? MAR
TDX
SHR (to ALU)
SHR
ACC ? BUS 1
BUS 3 ? ACC
SHL
SHL (to ALU)
29
Fetch
T4
RWD
Data flip-flop reset
WWD
from Execute logic
Input
S Q R
Output
S Q R
ACC to DOL
S Q R
30
Hardware Defer Logic
Defer
READ
T1
MBR ? BUS 2
T3
TRA2
BUS 3 ? MAR
31
Hardware Execute Logic
Execute
T1
LDA LDX ADD
READ
ACC ? BUS 1
TCA
COMP
BUS 3 ? ACC
1 ? BUS 1
TIX TDX
Index ? BUS 2
ADD
BUS 3 ? Index
-1 ? BUS 1
32
Execute
T1
MAR ? BUS 1
BRU
TRA1
BUS 3 ? PC
ACC ? BUS 1
STA
TRA1
BUS 3 ? MBR
MAR ? BUS 1
TRA1
BIP
BUS 3 ? PC
PSRN PSRZ
MAR ? BUS 1
TRA1
BIN
BUS 3 ? PC
Index ? BUS 2
STX
TRA2
BUS 3 ? MBR
33
Execute
T2
1 ? BUS 2
ACC ? BUS 1
TCA
ADD
BUS 3 ? ACC
BUS 2 15 BUS 2 14
MAR ? BUS 1
TRA1
BUS 3 ? PC
BUS 2 0
Index ? BUS 2
TIX
MAR ? BUS 1
TRA1
BUS 3 ? PC
Index ? BUS 2
TDX
WRITE
STA
WRITE
STX
34
Execute
T3
MBR ? BUS 2
LDA
TRA2
BUS 3 ? ACC
MBR ? BUS 2
LDX
TRA2
BUS 3 ? Index
MBR ? BUS 2
ADD
ACC ? BUS 1
BUS 3 ? Index
ADD
35
Execute
T4
DIL ? ACC
RWD
Data
Reset Input flip-flop
WWD
Reset Output flip-flop
Reset DOL flip-flop
36
Control Unit
MAR ? BUS 1 IR7-0 ? BUS 1 PC ? BUS 1 ACC ? BUS
1 Index ? BUS 2 MBR ? BUS 2
HLT
416 decoder
IR15
IR14
IR13
IR12
TDX
IR10
Clock
BUS 2
PSR