TimeBased ADCs

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Time-Based ADCs

• Seungwon Cho and Behzad Razavi

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Outline

• Concept of TDC
• Various topologies of TDCs
• Simple simulation on Delay based TDC
• High resolution TDCs

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Time to Digital conversion

• Small varactor for high linearity
• Narrow tuning range
• Need low phase noise

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TDC

• Things to consider
• resolution, linearity and dynamic range
• power consumption and area
• conversion speed, calibration procedure,
  buffering and read-out interface
• VCO tuning range 10GHz 11GHz
• TDC resolution at least 8-bits
• minimize power and area

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Outline

• Concept of TDC
• Various topologies of TDCs
• Stochastic TDC
• Cyclic TDC Pulse shrinking
• Vernier delay line TDC
• Coarse fine TDC
• Simple simulation on Delay based TDC
• High resolution TDCs

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Topologies of TDC
K. OK, Thesis 2005

• Stochastic TDC
• Utilizes the voltage offset of the two input of
  the arbiter
• Majority decision scheme
• Larger standard deviation ? larger dynamic range
  but lower resolution

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P. Chen et. al., JSSC 2005

• Cyclic TDC Pulse shrinking
• Merits of small die size, no continuous
  calibration requirement and very little power
  consumption
• It suffers from high temperature sensitivity and
  process variation

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P. Dudek et. al., 2000

• Vernier delay line ( similar to flash ADC )
• Small cost, high integration level compared to
  fast counters
• Area increases linearly with the resolution
• Devices must match more tightly ? high power
  consumption
• tRes t1 - t2
• tDR N tRes N number of delay element

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• Coarse - Fine TDCs
• Integer counter
• Counts VCO edges within a reference clock period
• Number of bits sets the TDC range
• Fractional counter
• Quantizes the residual phase, most critical block
• Number of bits sets the TDC resolution

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M. Lee et. al., JSSC 2008

• Coarse-Fine TDC that amplifies time residue
• Amplifies the residue between input and closest
  coarse level
• Quantizes the residue with the same coarse
  resolution
• Cons nonlinearity in the transfer function
  (input jitter to output jitter)

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Timing of TDC and decoded output

• ?? ? ?tr ? pseudo-thermometer code ? binary code
• Resolution ?tinv

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Delay Line
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SAFF

• Provides identical resolution for rising and
  falling edge metastability

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Decoder

• Detects first one to zero transition

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Results

• Resolution of 7ps ( ?tinv) ? need improvement
• Comparator
• Offset 32mV
• Power 2.8uW
• Overall system
• Resolution 8bits
• Sampling frequency 1GHz
• Power 4.1mW
• SAFF need to have higher resolution (offset,
  mismatch)
• Difficult to get constant resolution(delay chain
  mismatch)

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TDC Quantization Noise

• Assume quantization error has a uniform
  distribution and white spectrum
• To reduce phase noise (L)
• Improve resolution (?td), increase sampling
  frequency (fref)

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Time amplification based TDC
M. Lee et. al., JSSC 2008
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Principle of TA

• Initial voltage
• Output voltage difference

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Time offset

• Large Toff by introducing two inverters
• To compensate the gain loss, add more capacitance
  and reduce the gm of the Tr.

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XOR

• Outputs of the inverters stay low when X Y are
  around Vdd/2
• Simplified version
• XOR needs to detect only 10 pattern
• Dummy to balance the loading on the SR latch

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Thoughts

• Coarse TDC choices
• Counter
• Delay line TDC
• Fine TDC choices
• Vernier delay line
• Time amplification (should use Delay line TDC for
  the CTDC)
• Issues of TA based TDC
• Difficulty in controlling the gain of the TA
• Susceptible to process variations
• To do
• Mismatch issues in the TA ? calibration
• Compare calibration effort of TA and comparator
• Use both vernier delay line and TA?

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Motivation of interpolated TDC

• To get sub-gate delay resolution with low latency
  and low dead time
• Increases the resolution by the interpolating
  factor
• For normal delay line based TDCs, with large T
  and small TLSB, TDC becomes slow.

• Robust against process variations
• Global process variation ? can be cancelled out
  by digital post processing using normalization.
• Local process variations ? accumulate along the
  delay chain.

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Passive Time Interpolation TDC
S. Henzler et. al., JSSC 2008
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Passive resistors
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Pros and Cons

• Pros
• Sub-gate delay resolution while having low
  latency.
• Monotonic conversion characteristic
• Robust against local variations
• Cons
• Still have limitations because of local
  variations on comparators.(?)