Miniature Silicon Solar Cells

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Miniature Silicon Solar Cells
for
High Efficiency Tandem Cells

• Ngwe Soe Zin, Andrew Blakers

Evan Franklin, Vernie Everett
Australian National University
Centre of Sustainable Energy System
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Outline

• Purpose of the work
• Background of the Project
• Silicon Solar Cells for VHESC program
• Cell Design
• Design Considerations
• Target Efficiency
• Modelling and Characterisation
• Metal Plating
• IV Test Data
• Characterisation of Recombination
• Conclusion

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Purpose of the work

• Ultra-High efficiency solar cell devices are a
  major step forward in the development of low-cost
  PV technology
• Commercial applications, energy security, green
  house gas reductions, industry development
• Military applications, pollution reduction
• Potential trigger to revolutionise global
  electricity generation

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Background

• Solar cell efficiencies are approaching their
  practical efficiency limits

• Single junction 25 eff. in Si or GaAs (85 of
  practical efficiency)
• Tandem 38 for 3-stack under
• concentration (70 of practical efficiency)

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Background

• Very High Efficiency Solar Cell (VHESC) program
  works towards six-junction tandem solar cell
  stack approach
• VHESC integrates optics, interconnects, and cell
  designs
• Benefits
• Increased design space
• Increased theoretical efficiency
• Introduces options for new architectures
• Greater device design flexibility
• Reduced spectral mismatch losses
• Increased materials choices
• VHESC cells will be used in the mobile battery
  charging application

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Background (6-junction Tandem Stack)
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Cell Design

• Bifacial Cell
• N Contact at the Front
• P Contact at the Back

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Cell Design Considerations

• Illumination
• Light of energy lt1.42eV to Silicon
• Light of energy lt1.1eV to underlying cells
• BSR not an option
• Cell thickness should be 0.5-2mm for reasonable
  conversion efficiency for 875-1100nm

• IQE
• Diffusion length gtgt Cell thickness for more than
  90 IQE

• Resistive Losses
• 500µm thick cell will absorb 87 of the light
  (875-1100nm) in the top half of the cell
• Current sharing in bifacial cell will minimise
  resistive losses partially
• Electron current at the rear of diffused emitter
  will be small

• Recombination
• Thermal oxidation for Surface Recombination
• Cutting cells individually from the host wafer
  for Edge Recombination
• Contact is lt1 of total surface area for Contact
  Recombination

• Lateral Diffusive Losses
• Electron resistive loss is more concerned than
  that of hole since Rs of 500µm 1?cm ltlt Rs of
  Emitter Diffusion
• For estimated resistive loss of lt5, n contacts
  will be at both edges and ends of the cell
  (similar configuration for p contacts)

• Anti-Reflection
• Optimisation of oxide and nitride thickness to
  reduce reflection loss of
• 1 in air
• 3 under encapsulation

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Cell Efficiency
High Eg Cell
GaInP/GaAs
1.9 mm
1.9mm
Silicon
-

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Modelling

• Main Parameters Used for Modelling
• Active Area for 15mm
• Illumination at 1 sun intensity
• Bifacial Emitter as Active Region
• Heavy Phosphorous and Boron Diffusions

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Characterisation

• QSSPC technique was used to characterise
  effective carrier lifetime and emitter saturation
  current.

• Carrier lifetime after all high temperature step
  was maintained at around 560µs ( implied-Voc of
  640mV)
• Surface recombination was also remained low at
  around 25 fA/sq cm

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Metallisation

• metallisation of small contact with dimension of
  200µm x 5.5mm
• evaporated metal contacting method needs
• Fabrication of selective mask with opening only
  to contacts can tedious
• Alignment of mask to contact can be error-prone
• Misalignment can cause shading loss and shunting

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Metallisation

• Light-induced plating for n contacts
• Electrolyte plating for p contacts
• Both plating performed concurrently

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Metallisation

• Optical Microscope Measurement

AFM
Rate of Plating
p Contact
n Contact

• Assuming the conditions
• Current generated by light enters in the emitter
  equally
• Current enters the metal bus bar from one end and
  extracted from the other end

Power Loss ()
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Cells Making
LPCVD
Silicon Etch
TMAH Etch
RCA Clean
Si
Laser Scribe
Dicing
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I-V Testing

• Tested by flash-tester under 1 sun illumination
• Demonstrates the absence of shunt and good
  fill-factor
• Low Voc and Isc could be due to recombination at
  the emitter and cell edge (cells diced out of
  host wafer)
• Recombination due to cell edge unlikely since
  active region is at least 1mm away from cell edge

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Characterisation

• Recombination at the emitter region is suspected
• Experiment on dielectric using as etch mask and
  diffusion barrier

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Characterisation

• Experiment on dry etching (RIE) if it has impact
  on lifetime
• Results were compared against the earlier results

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Characterisation

• Samples deposited with nitride as etch mask or
  diffusion mask results in low lifetime compared
  to oxide
• Implied Voc was also observed lower for Sample
  using nitride as a etch mask
• Using nitride directly on top of silicon as etch
  mask or diffusion barrier may induce stress and
  thermal mismatch
• Samples etched by RIE to form emitter region has
  suffered drastic lifetime loss among all samples
• Ion damage caused by RIE on the silicon causes
  lifetime loss significantly

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Conclusion

• Cells fabricated present the absence of shunting
  and good fill-factor
• Low Voc and Isc for cells
• Possible factors causing low Voc and Isc were
  identified
• Subsequent batch of cell fabrication could
  increase the cell efficiency sharply

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Questions Answers