Processor: Datapath and Control

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Processor Datapath and Control

• Shivkumar Kalyanaraman
• Rensselaer Polytechnic Institute
• shivkuma_at_ecse.rpi.edu
• http//www.ecse.rpi.edu/Homepages/shivkuma

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Overview

• Datapath components and their interconnections
  used to implement the instruction set
  architecture
• Control implementation of signals used to
  control the information flow through the data
  path
• A single-cycle and multi-cycle implementation of
  a subset of the MIPS instruction set

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The Processor Datapath Control

• We're ready to look at an implementation of the
  MIPS
• Simplified to contain only
• memory-reference instructions lw, sw
• arithmetic-logical instructions add, sub, and,
  or, slt
• control flow instructions beq, j
• Generic Implementation
• use the program counter (PC) to supply
  instruction address
• get the instruction from memory
• read registers
• use the instruction to decide exactly what to do
• All instructions use the ALU after reading the
  registers

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Implementation Details

• Abstract / Simplified View
• Two types of functional units
• elements that operate on data values
  (combinational)
• elements that contain state (sequential)

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Building blocks combinatorial and sequential
logic

• An edge triggered methodology
• Typical execution
• read contents of some state elements,
• send values through some combinational logic
• write results to one or more state elements

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Building Blocks Register File

• Built using D flip-flops

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Building blocks Register File (contd)

• We still use the real clock to determine when to
  write

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Simple Implementation

• The functional units we need...

For instruction fetch
For lw and sw
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For arithmetic/logic operations
For beq
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Building the Datapath

• Use multiplexors to stitch them together

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Control

• Selecting the operations to perform (ALU,
  read/write, etc.)
• Controlling the flow of data (multiplexor inputs)
• Information comes from the 32 bits of the
  instruction
• Example add t0, s1, s2 add 8, 17, 18
• Instruction Format 000000 10001 10010
  01000 00000 100000
• op rs rt rd shamt funct
• ALU's operation based on instruction type and
  function code

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Control

• Example lw 1, 100(2)
• 35 2 1 100 op
  rs rt 16 bit offset
• ALU hardware control input 000
  AND 001 OR 010 add 110 subtract 111 set-on-le
  ss-than

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Control

• Need hardware to compute 3-bit ALU control input
• given instruction type compute ALUOp 00 lw,
  sw 01 beq, 11 arithmetic
• function code determines arithmetic signals
• Describe it using a truth table (can turn into
  gates)

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Control implementation

• Simple combinational logic (truth tables)

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Single Cycle Implementation

• Calculate cycle time assuming negligible delays
  except
• memory (2ns), ALU adders (2ns), register file
  (1ns)

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Where we are headed

• Single Cycle Problems
• what if we had more complicated things like
  floating point?
• wasteful of area, and cycle time that of
  slowest instruction
• One Solution
• Use a smaller cycle time
• Have different instructions take different
  numbers of cycles
• A multicycle datapath

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Multicycle Approach

• We will be reusing functional units
• Single ALU used to compute address and to
  increment PC
• Single memory used for instruction and data
• Control signals not determined solely by
  instruction
• It also will depend upon the current cycle of
  execution
• Well use a finite state machine for control

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Review finite state machines

• Finite state machines
• a set of states and
• next state function (determined by current state
  and the input)
• output function (determined by current state and
  possibly input)
• Well use a Moore machine (output based only on
  current state)

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Multicycle Approach

• Break up the instructions into steps, each step
  takes a cycle
• restrict each cycle to use only one major
  functional unit
• At the end of a cycle
• store values for use in later cycles (easiest
  thing to do)
• introduce additional internal registers

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Multicycle Approach
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Five Execution Steps

• Instruction Fetch
• Instruction Decode and Register Fetch
• Execution, Memory Address Computation, or Branch
  Completion
• Memory Access or R-type instruction completion
• Write-back step INSTRUCTIONS TAKE FROM 3 - 5
  CYCLES!

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Step 1 Instruction Fetch

• Use PC to get instruction and put it in the
  Instruction Register.
• Increment the PC by 4 and put the result back in
  the PC.
• Can be described succinctly using RTL
  "Register-Transfer Language" IR
  MemoryPC PC PC 4What is the advantage
  of updating the PC now?

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Step 2 Instruction Decode and Register Fetch

• Read registers rs and rt in case we need them
• Compute the branch address in case the
  instruction is a branch
• RTL A RegIR25-21 B
  RegIR20-16ALUOut PC (sign-extend(IR15-0
  ) ltlt2)
• We aren't setting any control lines based on the
  instruction type. We are busy "decoding" it in
  our control logic.

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Step 3 (instruction dependent)

• ALU is performing one of three functions, based
  on instruction type
• Memory Reference ALUOut A
  sign-extend(IR15-0)
• R-type ALUOut A op B
• Branch if (AB) PC ALUOut

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Step 4 (R-type or memory-access)

• Loads and stores access memory MDR
  MemoryALUOut or MemoryALUOut B
• R-type instructions finish RegIR15-11
  ALUOutThe write actually takes place at the
  end of the cycle on the edge

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Write-back step

• RegIR20-16 MDR
• What about all the other instructions?

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Summary
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Simple Questions

• How many cycles will it take to execute this
  code? lw t2, 0(t3) lw t3, 4(t3) beq
  t2, t3, Label assume not equal add t5, t2,
  t3 sw t5, 8(t3)Label ...
• In what cycle does the actual addition of t2 and
  t3 takes place?

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Implementing the Control

• Value of control signals is dependent upon
• what instruction is being executed
• which step is being performed
• Use the information weve accumulated to specify
  a finite state machine
• specify the finite state machine graphically, or
• use microprogramming(specify control information
  as a program)
• Implementation can be derived from specification

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Graphical Specification of FSM

• How many state bits will we need?

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Finite State Machine for Control

• Implementation

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PLA Implementation

• If I picked a horizontal or vertical line could
  you explain it?

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Microprogramming

• A specification methodology
• appropriate if hundreds of opcodes, modes,
  cycles, etc.
• signals specified symbolically using
  microinstructions
• Will two implementations of the same architecture
  have the same microcode?
• What would a microassembler do?

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Microinstruction format
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Microprogram Implementation

• The "next state" is often current state 1
• Dispatch tables used if explicit jump needed

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The Big Picture for control
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Summary

• Datapath components, single- and multi-cycle
  implementation for MIPS subset
• Single cycle CPI 1, clock cycle large
• Multi-cycle CPI variable, clock cycle small
• Control Simple for single-cycle, complex (need
  FSM or microprogram) for multi-cycle
  implementation