Chapter Five The Processor: Datapath and Control

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Chapter FiveThe Processor Datapath and Control
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The Processor Datapath Control

• We're ready to look at an implementation of the
  MIPS
• Simplified to contain only
• memory-reference instructions lw, sw
• arithmetic-logical instructions add, sub, and,
  or, slt
• control flow instructions beq, j

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Generic Implementation

• use the program counter (PC) to supply
  instruction address
• get the instruction from memory
• read registers
• use the instruction to decide exactly what to do
• All instructions use the ALU after reading the
  registers
• Why? memory-reference? arithmetic? control
  flow?

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More Implementation Details

• Abstract / Simplified ViewTwo types
  of functional units
• elements that operate on data values
  (combinational)
• elements that contain state (sequential)

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State Elements

• Unclocked vs. Clocked
• Clocks used in synchronous logic
• when should an element that contains state be
  updated?

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An unclocked state element

• The set-reset latch
• output depends on present inputs and also on past
  inputs

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Latches and Flip-flops

• Latches and flip-flops are the simplest memory
  elements.
• Output is equal to the stored value inside the
  element(don't need to ask for permission to look
  at the value)
• Change of state (value) is based on the clock
• Latches whenever the inputs change, and the
  clock is asserted
• Flip-flop state changes only on a clock
  edge (edge-triggered methodology)

A clocking methodology defines when signals can
be read and written Wouldn't want to read a
signal at the same time it was being written
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D-latch

• Two inputs
• the data value to be stored (D)
• the clock signal (C) indicating when to read
  store D
• Two outputs
• the value of the internal state (Q) and it's
  complement
• When the latch is open (C asserted), the value of
  Q changes as D changes? transparent latch.

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D flip-flop

• Flip-flops are not transparent
• Output changes only on the clock edge
• The first latch, called the master, is open and
  follows the input D when C is asserted. When the
  clock input falls, the first latch is closed, but
  the 2nd latch, called the slave, is open and gets
  its input from the output of the master latch.

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Set-up time and Hold time

• Set-up time the minimum time that the input must
  remain valid before the clock edge
• Hold time the minimum time that the input must
  be valid after the clock edge (usually very
  small)

D
Set-up time
Hold time
C
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Our Implementation

• An edge triggered methodology
• Typical execution
• read contents of some state elements,
• send values through some combinational logic
• write results to one or more state elements

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Register File

• A register file consists of a set of registers
  that can be read and written by supplying a
  register number to be accessed.
• Built using D flip-flops and decoders (specify
  register number)
• Read part (left) supply a register number as
  input, and the output is the information stored
  in that register.
• A register file with 2 read ports and 1 write
  ports. (right)

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Register File

• Write part need 3 inputs a register number, the
  data to write, and a clock that controls the
  writing into the register.
• Note we still use the real clock to determine
  when to write

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Simple Implementation

• Basic components
• two state elements instruction memory and program
  counter are needed to store and access
  instructions.
• An adder is needed to compute the next
  instruction address.
• Since the instruction memory is read-only, we can
  treat it as combinational logic.

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Fetching instruction and incrementing PC

• A portion of the datapath used for fetching
  instructions and incrementing Program Counter

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R-Format ALU operations

• R-format instruction has 3 register operands, 2
  read and 1 write

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Datapath for R-type Instruction

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Load and Store Instructions

• Load and store instructions compute a memory
  address by adding the base register, to a 16-bit
  signed offset field contained in the instruction.

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Datapath for load and store instructions

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J-type Instruction

• Branch datapath
• Needs to compute the branch target address
• PC4 is the address of the next instruction
• Offset field is left-shifted two bits to make a
  word offset.
• Needs to compare register contents

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Branch Datapath

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Building the Datapath
Use multiplexors to stitch them together