Designing MIPS Processor (Multi-Cycle) Presentation H

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CSE 675.02 Introduction to Computer Architecture
Designing MIPS Processor(Multi-Cycle)
Presentation H
Slides by Gojko Babicand Elsevier Publishing
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Multicycle Approach

• We will be reusing functional units
• ALU used to compute address and to increment PC
• Memory used for instruction and data
• Our control signals will not be determined
  directly by instruction
• e.g., what should the ALU do for a subtract
  instruction?
• Well use a finite state machine for control

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Multicycle Approach

• Break up the instructions into steps, each step
  takes a cycle
• balance the amount of work to be done
• restrict each cycle to use only one major
  functional unit
• At the end of a cycle
• store values for use in later cycles (easiest
  thing to do)
• introduce additional internal registers

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Instructions from ISA perspective

• Consider each instruction from perspective of
  ISA.
• Example
• The add instruction changes a register.
• Register specified by bits 1511 of instruction.
  
• Instruction specified by the PC.
• New value is the sum (op) of two registers.
• Registers specified by bits 2521 and 2016 of
  the instruction RegMemoryPC1511 lt
  RegMemoryPC2521 op
  RegMemoryPC2016
• In order to accomplish this we must break up the
  instruction. (kind of like introducing variables
  when programming)

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Breaking down an instruction

• ISA definition of arithmeticRegMemoryPC151
  1 lt RegMemoryPC2521 op
  RegMemoryPC2016
• Could break down to
• IR lt MemoryPC
• A lt RegIR2521
• B lt RegIR2016
• ALUOut lt A op B
• RegIR2016 lt ALUOut
• We forgot an important part of the definition of
  arithmetic!
• PC lt PC 4

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Idea behind multicycle approach

• We define each instruction from the ISA
  perspective (do this!)
• Break it down into steps following our rule that
  data flows through at most one major functional
  unit (e.g., balance work across steps)
• Introduce new registers as needed (e.g, A, B,
  ALUOut, MDR, etc.)
• Finally try and pack as much work into each step
  (avoid unnecessary cycles)while also trying to
  share steps where possible (minimizes control,
  helps to simplify solution)
• Result Our books multicycle Implementation!

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Five Execution Steps

• Instruction Fetch
• Instruction Decode and Register Fetch
• Execution, Memory Address Computation, or Branch
  Completion
• Memory Access or R-type instruction completion
• Write-back step INSTRUCTIONS TAKE FROM 3 - 5
  CYCLES!

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Step 1 Instruction Fetch

• Use PC to get instruction and put it in the
  Instruction Register.
• Increment the PC by 4 and put the result back in
  the PC.
• Can be described succinctly using RTL
  "Register-Transfer Language" IR lt
  MemoryPC //PC lt PC 4 ALUOut lt PC
  4Can we figure out the values of the control
  signals?What is the advantage of updating the
  PC now?

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Step 2 Instruction Decode and Register Fetch

• Read registers rs and rt in case we need them
• Compute the branch address in case the
  instruction is a branch
• RTL A lt RegIR2521 B lt
  RegIR2016 ALUOut lt PC
  (sign-extend(IR150) ltlt 2)
• We aren't setting any control lines based on the
  instruction type (we are busy "decoding" it in
  our control logic)

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Step 3 (instruction dependent)

• ALU is performing one of three functions, based
  on instruction type
• Memory Reference ALUOut lt A
  sign-extend(IR150)
• R-type ALUOut lt A op B
• Branch if (AB) PC lt ALUOut

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Step 4 (R-type or memory-access)

• Loads and stores access memory MDR lt
  MemoryALUOut or MemoryALUOut lt B
• R-type instructions finish RegIR1511 lt
  ALUOutThe write actually takes place at the
  end of the cycle on the edge

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Write-back step

• RegIR2016 lt MDR
• Which instruction needs this?

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Summary
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Simple Questions

• How many cycles will it take to execute this
  code? lw t2, 0(t3) lw t3, 4(t3) beq
  t2, t3, Label assume not add t5, t2,
  t3 sw t5, 8(t3)Label ...
• What is going on during the 8th cycle of
  execution?
• In what cycle does the actual addition of t2 and
  t3 takes place?

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Review finite state machines

• Finite state machines
• a set of states and
• next state function (determined by current state
  and the input)
• output function (determined by current state and
  possibly input)
• Well use a Moore machine (output based only on
  current state)

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Finite State Machines Introduction
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Review finite state machines

• Example B. 37 A friend would like you to
  build an electronic eye for use as a fake
  security device. The device consists of three
  lights lined up in a row, controlled by the
  outputs Left, Middle, and Right, which, if
  asserted, indicate that a light should be on.
  Only one light is on at a time, and the light
  moves from left to right and then from right to
  left, thus scaring away thieves who believe that
  the device is monitoring their activity. Draw
  the graphical representation for the finite state
  machine used to specify the electronic eye. Note
  that the rate of the eyes movement will be
  controlled by the clock speed (which should not
  be too great) and that there are essentially no
  inputs.

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Finite State Machine Example 3 ones
Draw the FSM
Truth table
PS Input NS Output
00 0 00 0
00 1 01 0
01 0 00 0
01 1 10 0
10 0 00 0
10 1 00 1
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Hardware Implementation of FSM


?
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Implementing the Control

• Value of control signals is dependent upon
• what instruction is being executed
• which step is being performed
• Use the information weve accumulated to specify
  a finite state machine
• specify the finite state machine graphically, or
• use microprogramming
• Implementation can be derived from specification

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Graphical Specification of FSM

• Note
• dont care if not mentioned
• asserted if name only
• otherwise exact value
• How many state bits will we need?

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Step 1 Instruction Fetch

• Use PC to get instruction and put it in the
  Instruction Register,
• i.e. IR ? MemoryPC
• Increment the PC by 4 and put the result back in
  the PC,
• i.e. PC ? PC 4
• Can we figure out the values of the control
  signals?
• Here are rules for signals that are omitted
• If signal for mux is not stated, it is dont care
• If ALU signals are not stated, they are dont
  care
• If MemRead, MemWrite, RegWrite, IRWrite, PCWrite
  or PCWriteCond is not stated, it is unasserted,
  i.e. logical 0.

IorD0, MemRead, IRWrite
ALUSrcA0, ALUSrcB01, ALUOp00, PCSource0,
PCWrite
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Step 2 Instruction Decode Register Fetch

• We aren't setting any control lines based on the
  instruction type (we are busy "decoding" it in
  our control logic)
• Read registers rs and rt in case we need them
• A ? RegIR25-21B ? RegIR20-16
• Done automatically
• Compute the branch address in case the
  instruction is a branch
• ALUOut ? PC (sign-extend(IR15-0) ltlt 2)
• ALUSrcA0, ALUSrcB11, ALUOp00

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Step 3 Instruction Dependent

• ALU is performing one of three functions, based
  on instruction type
• Memory Reference (lw or sw) ALUOut ? A
  sign-extend(IR15-0)
• R-type ALUOut ? A op B
• Branch on Equal if (AB) PC ? ALUOut

ALUSrcA1, ALUSrcB10, ALUop00
ALUSrcA1, ALUSrcB00, ALU0p10
ALUSrcA1, ALUSrcB00, ALU0p01 PCSource01,
PCWriteCond
Note beq instruction is done, thus this
instruction requires 3 clock cycles to execute.
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Steps 4 and 5 Instruction Dependent

• Step 4 R-type and Memory Access
• Loads and stores access memory MDR ?
  MemoryALUOut (load) or MemoryALUOut ? B
  (store)
• R-type instructions finish RegIR15-11 ?
  ALUOut
• Register write actually takes place at the end
  of the cycle on the falling edge
• Store and R-type instructions are done in 4 clock
  cycles
• Step 5 Write back (load only)
• RegIR20-16 ? MDR

IorD1, MemRead
IorD1, MemWrite
RegDst1, MemToReg0, RegWrite
RegDst0, MemToReg1, RegWrite
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Summary of Instruction Executions
Figure 5.50
Note Jump instruction added
PCSource10, PCWrite
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Finite State Machine for Control

• Implementation

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PLA Implementation
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ROM Implementation

• ROM "Read Only Memory"
• values of memory locations are fixed ahead of
  time
• A ROM can be used to implement a truth table
• if the address is m-bits, we can address 2m
  entries in the ROM.
• our outputs are the bits of data that the address
  points to.m is the "height", and n is
  the "width"

0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 0 1 1 1
0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 1
0 1 1 1 0 1 1 1
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ROM Implementation

• How many inputs are there? 6 bits for opcode, 4
  bits for state 10 address lines (i.e., 210
  1024 different addresses)
• How many outputs are there? 16 datapath-control
  outputs, 4 state bits 20 outputs
• ROM is 210 x 20 20K bits (and a rather
  unusual size)
• Rather wasteful, since for lots of the entries,
  the outputs are the same i.e., opcode is often
  ignored

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ROM vs PLA

• Break up the table into two parts 4 state bits
  tell you the 16 outputs, 24 x 16 bits of
  ROM 10 bits tell you the 4 next state bits,
  210 x 4 bits of ROM Total 4.3K bits of ROM
• PLA is much smaller can share product terms
  only need entries that produce an active
  output can take into account don't cares
• Size is (inputs product-terms) (outputs
  product-terms) For this example
  (10x17)(20x17) 510 PLA cells
• PLA cells usually about the size of a ROM cell
  (slightly bigger)

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Another Implementation Style

• Complex instructions the "next state" is often
  current state 1

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Details
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Microprogramming

• What are the microinstructions ?

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Microprogramming

• A specification methodology
• appropriate if hundreds of opcodes, modes,
  cycles, etc.
• signals specified symbolically using
  microinstructions
• Will two implementations of the same architecture
  have the same microcode?
• What would a microassembler do?

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Microinstruction format
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Maximally vs. Minimally Encoded

• No encoding
• 1 bit for each datapath operation
• faster, requires more memory (logic)
• used for Vax 780 an astonishing 400K of memory!
• Lots of encoding
• send the microinstructions through logic to get
  control signals
• uses less memory, slower
• Historical context of CISC
• Too much logic to put on a single chip with
  everything else
• Use a ROM (or even RAM) to hold the microcode
• Its easy to add new instructions

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Microcode Trade-offs

• Distinction between specification and
  implementation is sometimes blurred
• Specification Advantages
• Easy to design and write
• Design architecture and microcode in parallel
• Implementation (off-chip ROM) Advantages
• Easy to change since values are in memory
• Can emulate other architectures
• Can make use of internal registers
• Implementation Disadvantages, SLOWER now that
• Control is implemented on same chip as processor
• ROM is no longer faster than RAM
• No need to go back and make changes

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Historical Perspective

• In the 60s and 70s microprogramming was very
  important for implementing machines
• This led to more sophisticated ISAs and the VAX
• In the 80s RISC processors based on pipelining
  became popular
• Pipelining the microinstructions is also
  possible!
• Implementations of IA-32 architecture processors
  since 486 use
• hardwired control for simpler instructions
  (few cycles, FSM control implemented using PLA
  or random logic)
• microcoded control for more complex
  instructions (large numbers of cycles, central
  control store)
• The IA-64 architecture uses a RISC-style ISA and
  can be implemented without a large central
  control store

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Pentium 4

• Pipelining is important (last IA-32 without it
  was 80386 in 1985)
• Pipelining is used for the simple instructions
  favored by compilersSimply put, a high
  performance implementation needs to ensure that
  the simple instructions execute quickly, and that
  the burden of the complexities of the instruction
  set penalize the complex, less frequently used,
  instructions

Chapter 7
Chapter 6
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Pentium 4

• Somewhere in all that control we must handle
  complex instructions
• Processor executes simple microinstructions, 70
  bits wide (hardwired)
• 120 control lines for integer datapath (400 for
  floating point)
• If an instruction requires more than 4
  microinstructions to implement, control from
  microcode ROM (8000 microinstructions)
• Its complicated!

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Chapter 5 Summary

• If we understand the instructions We can build
  a simple processor!
• If instructions take different amounts of time,
  multi-cycle is better
• Datapath implemented using
• Combinational logic for arithmetic
• State holding elements to remember bits
• Control implemented using
• Combinational logic for single-cycle
  implementation
• Finite state machine for multi-cycle
  implementation

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MIPS Exception Processing
We are implementing processing of the following
two exceptions illegal op- code and integer
overflow. When any of the exceptions occurs, MIPS
processor processes the exception in the
following 3 steps Step 1. EPC register gets a
value equal to address of a faulty
instruction. Step 2. PC ? 8000018016 Cause
register ? a code of the exception
illegal op-code, i.e. reserved or undefined
op-code 10 integer overflow 12 Step
3. Processor is now running in Kernel mode.
Note we are not implementing step 3.
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Multi-Cycle Datapath for Exception Handling
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Figure 5.39 with corrections in red
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FSM Graph with Exception Handling
Figure 5.40 with additions in red