Manufacturability, Test, and Diagnostics for Microelectronics

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Manufacturability, Test, and Diagnostics for
Microelectronics

• Summer Semester 2008Dr. Bernd KoenemannProf.
  Dr. Walter AnheierDr. Ajoy Palit

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Overall Context
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Today ATPG
Faults
ATPG/Fault-Grading
Netlist
Test Data
FaultCoverage
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Automatic Test Pattern Generation

• ATPG
• Algorithmic generation of test patterns for model
  faults
• Requires netlist and fault list of the circuit
  under test
• Objective is to generate a set of test patterns
  that is capable of detecting as many faults in
  the fault list as possible
• Ideally all faults are tested (100 fault
  coverage)
• ATPG typically alternates between
• Constructive pattern generation for one or
  several untested faults at a time
• Fault simulation to determine if other untested
  faults are also tested

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ATPG Terminology

• Primary Input (PI)
• Primary Output (PO)
• Target fault
• Fault excitation/activation
• Fault propagation
• Objective
• Backtrace
• Justification

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ATPG Terminology (ctd)

• Implication
• Decision
• Decision Stack
• Conflict
• Backtracking/Decision Re-make
• Test-Cube
• Compaction
• (Pattern) Fill
• Test Pattern

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Intermezzo Test Requirements

• Chip Manufacturing Tests
• To achieve low defect levels typically requires
• 99 stuck-at fault coverage
• Iddq and/or at-speed tests to avoid delay defect
  escapes (technology/design dependent)
• Iddq test and/or burn-in to reduce early life
  fails
• Assembly manufacturing tests (e.g., for circuit
  boards)
• Assembly defects
• 100 shorts/opens coverage of chip attach and
  interconnect
• Chip damage (handling, stress, early life fails)
• 85-90 stuck-at fault coverage can be sufficient
• Note bare chips are more sensitive than packaged
  chips
• Passive Components
• Verify presence and proper values of resistors,
  capacitors, etc.

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Intermezzo Diagnostics Requirements

• Diagnostics For Chip Manufacturing
• Enable physical failure analysis
• Identify failing logic gates/nets or memory cells
  to help rapid yield learning (important for new
  technologies)
• Enable repair for large embedded memories
• Identify failing memory cells to guide row/column
  replacement
• Diagnostics For Assembly Manufacturing
• Enable repair
• Identify failing interconnect for substrate
  repair
• Identify failing components for replacement
• Avoid unnecessary damage
• Enable single pass diagnosis/repair of multiple
  defects for assemblies with limited re-work
  cycles (e.g., MCMs)
• Repair interconnect shorts before they damage
  good chips

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ATPG for Combinational Logic

• Relatively easy
• Can justify/propagate directly at/to PIs/Pos
• Known algorithms achieve high fault coverage

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ATPG for Sequential Circuits

• Much more complicated
• Must propagate/justify through state-elements
• Need multiple time images (e.g., unroll logic
  multiple times)
• No really good algorithms are known
• Long run times, insufficient fault coverage

PIs
POs
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Overall Context
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DFT

• DFT Design for Test or Design for Testability
• Enables test automation by
• Removing complex sequential behavior for
  Automatic Test Pattern Generation (ATPG)
• Implementing test infrastructures for various
  circuit structures and embedded modules
• Supports rapid debug and diagnostics by
• Providing access (control/observation) of
  otherwise hidden internal states

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DFT Basics Scan

• Scan design Is the most widely used basic DFT
  method for complex logic
• Scan adds a special mode of operation in which
  internal registers are loaded/unloaded via a
  simple serial interface

Logic
Logic
Registers
Registers
serial interface
Without Scan Registers are hidden inside
product under test and cannot be accessed directly
With Scan Registers can be loaded/ unloaded
easily using a simple serial interface
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Scannable Registers

• Replace the register elements with scan cells
• Most popular style uses multiplexed scan
  Flip-Flops
• Scan Flip-Flops are available in most commercial
  ASIC libraries
• Other types of scan cells may also be offered
• Supported by automatic scan insertion tools

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Scan Paths

• Connect scan cells into shift-register chains
• External pins Scan In, Scan Out, Scan Enable,
  Clock
• Shift-in/out operation (scan mode) is independent
  of logic function

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Scan-Based Testing

• Use scan paths to access combinational logic
  between registers for test
• Basic scan test protocol1. Load test input
  data into internal registers (scan mode)2. Set
  up any required external input conditions3. Let
  data propagate through combinational logic4.
  Measure external output responses5. Capture
  internal responses into registers (system clock)
  6. Unload responses from registers (scan mode)
• Scannable register elements are virtual PIs/POs
  for efficient combinational or near-combinational
  ATPG algorithms

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Scan Design Statistics

• Number of logic gates versus number of scan cells
• Rule of thumb 500 scan cells per 10,000 gates
• But can vary by design type

Examples Mentor Graphics Corp.
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Scan Test Characteristics

• Advantages
• Enables highly automated test development
• Largely design and technology independent (test
  engineer does not have to understand design
  function)
• Supported By Powerful Commercial DFT and ATPG
  Tools
• Automatic insertion and connection of scan cells,
  automated checking of scan design rules,
  high-performance ATPG tools
• Excellent diagnostics
• Disadvantages
• Some silicon and performance overhead
• Data volumes can be extremely high for complex
  chips
• Requires deep tester memory for scan I/O pins
• Slow test throughput with long scan chains
• Use multiple shorter chains for testing complex
  chips

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Scan Design Considerations

• Scan cell types
• e.g., edge-triggered, level-sensitive
• Timing considerations
• e.g., set-up/hold-time issues, etc.
• Scan chain construction
• e.g., ordering, physical design impact, timing
  robustness, etc.

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Flip-Flops and Latches

• Flip-flops are edge-sensitive
• Propagate and capture on positive or negative
  edge
• Latches are level-sensitive
• Propagate when clock is active, hold when clock
  is off

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Clock-Data Race at Storage Elements

• Flip-Flops, latches are exposed to clock-data
  races
• New data must arrive setup-time prior to clock
  edge to be stored
• Data must remain stable until hold-time after
  clock to maintain stored value

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Clock Skew

• Clock edges do not arrive at all storage elements
  at exactly the same time
• Caused by statistical and/or systematic
  variations between clock distribution paths
• Edge arrival time differences (skew) must be
  considered during the design of safe data
  transfers between storage elements
• Can affect functional operation and/or scan
  operations
• Clock skew impacts performance and safe data
  transfer
• Must be subtracted from available signal
  propagation times for set-up requirement
• Must be added to required signal stability times
  for hold-time requirement

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Skew and Edge-Triggered Scan

• Clock edge should capture data waiting on inputs
• Data delay be larger than hold-time plus skew
• Extra delay (combinational padding or
  re-timing/lock-up element) may have to be
  inserted for safe operation
• Note Slowing down clocks does not help

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Level-Sensitive Scan

• Uses multi-phase clocking with non-overlapped
  clocks to avoid hold-time problems during scan
• Clock separation acts like delay padding

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Scan Cell Types

• Scan cells can be implemented in several ways,
  e.g.,
• Externally or Internally multiplexed
• Different clocking styles
• Edge-triggered versus multi-phase
• May differ between scan and system operation
  (e.g., multi-phase scan with edge-triggered
  capture)

Scan-Enable
Latch Or Flip-Flop
Latch Or Flip-Flop
SysData
SysData
0
SysClk
ScnData
1
ScnData
ScnClk
Clock
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Clock-Multiplexed Scan Latch Example

• Scan/data multiplexing is integrated inside the
  latch
• Advantage No added devices in data path
• Disadvantage needs more complex clock drivers
• Weak inverter (shown) or clocked inverter for
  feedback

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Inter-domain Hold-Time Issues

• Depending on skew, new value captured in FF1 may
  or may not propagate to FF2
• Unpredictable capture in FF2
• NOTE hold-time problems affect slow static tests
  as well as at-speed tests

Interfacelogic
FF1
FF1
skew
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Capture by Domain

• DFT guidelines may recommend different test
  clocks and ATPG capture data only in one domain
  at a time
• Inefficient testing adds to test data volume and
  test time
• Newer ATPG tools have multi-clock compaction
  options
• Issue several independent domain clocks together
• Sequence domain clocks for guaranteed hold-time
  resolution (sequential behavior)

Interfacelogic
FF1
FF1
TestClk2
TestClk1
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Lock-Up Latches

• Lock-up or re-timing latches hold signal changes
  back for half a cycle to overcome hold-time
• Note skew must be smaller than half cycle
• Lock-up latch at source shown in example
• Impacts functional data path

Interfacelogic
FF1
FF1
skew
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Test Synthesis

• Automatic insertion of scan paths during logic
  synthesis and physical design
• Must account for timing considerations (e.g.,
  clock domains, delay padding, lock-up latches,
  etc.)
• Must account for test economy (e.g., number and
  length of scan paths, sharing of functional and
  test pins)
• Must account for physical design impact (e.g.,
  wireability of scan paths and test controls)

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Un-optimized Scan
RTL
Synthesis Scan Insertion
PR
ATPG
Source Synopsys (Note modified from original)
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Optimized Scan
Source Synopsys
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Our Agenda for the SEmester